3mo
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ASIC Verification Engineer
Austin, Texas, United States
$116k-$190k/yr HybridFull Time
2+ YOEBS/MS in Electrical or Computer Engineering; 2+ years ASIC/RTL verification; pre-silicon verification (UVM, SystemVerilog); RTL verification; Perl/Python; debugging; exposure to verification tools; strong communication.
UVM, SystemVerilog, Perl, Python, dc_shell, VCS, GDB, Debussy
1mo
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Senior ASIC Verification Engineer
Austin, Texas, United States
$136k-$265k/yr HybridFull Time
5+ YOEBS/MS in Electrical or Computer Engineering (or equivalent), 5+ years design verification experience, UVM/SystemVerilog, ASIC flow, Perl or Python, familiarity with synthesis/simulation and debug tools.
SystemVerilog, UVM, Perl, Python, dc_shell, VCS, Debussy, GDB
1mo
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Experienced Engineer - ASIC Verification
Chennai or Bangalore or Sweden or United States
OnsiteFull Time
5+ YOEBachelor's in electrical/computer engineering; 5+ years ASIC IP verification with SystemVerilog and UVM; experience with AXI/CHI and SystemVerilog Assertions; familiarity with Cadence/Synopsys; strong English and teamwork skills.
SystemVerilog, UVM, SystemVerilog Assertions, AMBA, AXI, CHI, Cadence, Synopsys, Jenkins, Simscope, Jira
2mo
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
6+ YOEBachelor's or Master's in Electrical/Computer Engineering; 6-10 years VLSI design/verification; Verilog/SystemVerilog/UVM; scripting (Python/Perl/TCL); C/C++; EDA/verification tools.
Verilog, SystemVerilog, UVM, Specman, Python, Perl, TCL, C, C++, EDA tools
3mo
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Principal ASIC verification engineer
Durham, North Carolina, United States
$153k-$353k/yr HybridFull Time
10+ YOESenior hardware engineer with VLSI/ASIC verification expertise; 10+ years experience; degree in Electrical or Computer Engineering (Bachelor/Master/PhD)
HDL, Verilog, VHDL, SystemVerilog, EDA tools, FPGA, Python, C++
3w
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Staff Engineer - ASIC Verification
San Jose, California, United States
$139k-$259k/yr HybridFull Time
8+ YOEBachelor's in CS/EE required (Master's desired), 8+ years ASIC verification experience, fluent in System Verilog, UVM, Python/Perl, knowledge of assertions, functional/code coverage and formal verification tools, strong communication.
System Verilog, UVM, Python, Perl
1mo
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Sr. ASIC Verification Engineer
Sunnyvale or Munich
OnsiteFull Time
4+ YOE4+ years ASIC verification experience; expert in SystemVerilog/UVM, constraint-random and coverage-driven verification; experience with C/C++/SystemC, high-speed interfaces, scripting (Python/Perl/TCL/Shell), and post-silicon validation; BS required, MS preferred.
SystemVerilog, UVM, C, C++, SystemC, Python, Perl, TCL, Shell, ARM, RISC-V, PCIe, Ethernet, DDR, HBM, SerDes
1mo
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ASIC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years verification experience, 2+ full block/system verification cycles, deep VLSI verification knowledge, experience with SystemVerilog/UVM/eRM, familiarity with data-paths/protocols (Ethernet preferred), mentoring and cross-team collaboration.
SystemVerilog, UVM, eRM, RTL, Ethernet
2mo
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
6+ YOE6-10 years in VLSI design/verification; BS/MS in Electrical or Computer Engineering; scripting (Python/Perl/TCL); programming (C/C++); Verilog/SystemVerilog; UVM; knowledge of EDA tools.
Verilog, SystemVerilog, UVM, Python, Perl, TCL, C, C++
2mo
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ASIC Verification Engineer
San Jose, California, United States
OnsiteFull Time
8+ YOE8+ years in UVM verification; RTL/gate-level verification; test plan and testbench development in C/Assembly/SystemVerilog; AMBA AXI/AHB/APB; PCIe/USB/Ethernet; scripting; repository and bug-tracking tools.
UVM, SystemVerilog, C, Assembly, Python, Shell, Perl, AMBA AXI, AHB, APB, PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, Git, JIRA, Bitbucket, Jenkins
3mo
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ASIC Design Verification Engineer
United States
$200k-$350k/yr RemoteFull Time
8+ YOE8+ years ASIC verification; degree in EE/CE; SystemVerilog UVM; testbenches and coverage-driven verification; experience with EDA tools; scripting (Python/Perl/TCL).
SystemVerilog, UVM, Simulation tools, Cadence tools, Synopsys tools, Mentor Graphics tools, Python, Perl, TCL
2d
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SR ASIC Design Verification Engineer
San Jose, California, United States
$165k-$241k/yr OnsiteFull Time
1+ YOEDegree in electrical/computer engineering or related plus multi-year ASIC verification experience; proficiency in System Verilog and UVM; ASIC verification, simulation, emulation, post-silicon debug experience; Linux and programming (C/C++, Python/Perl).
System Verilog, UVM, Veloce, Palladium, Zebu, HAPS, Linux, C/C++, Python/Perl
3mo
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Sr. Staff ASIC Verification Engineer
Palo Alto, California, United States
$237k-$296k/yr OnsiteFull Time
10+ YOETypically 10+ years in ASIC design verification; BS/MS or PhD in Electrical or Computer Engineering; deep computer architecture; NoC; UPF/CPF; Systolic Arrays/NPUs; CNN/Transformer mapping; compilers/toolchains.
SystemVerilog, UVM, SVA, ISO 26262, FIA, Emulation, FPGA
1mo
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Senior Engineer - ASIC Verification (786546)
Bengaluru or Chennai or India or Sweden or United States
OnsiteFull Time
10+ YOEBachelor's in electrical/computer engineering, 10+ years ASIC IP verification using SystemVerilog and UVM, experience with AMBA/AXI/CHI and SystemVerilog Assertions, Cadence/Synopsys tool experience, strong communication and attention to detail.
SystemVerilog, UVM, AMBA, AXI, CHI, SystemVerilog Assertions, Cadence, Synopsys, Jenkins, Simscope, Jira
22h
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ASIC Verification Engineer (Remote)
Williston, Vermont, United States
$120k-$165k/yr RemoteFull Time
10+ YOE10+ years verification experience, BS/MS in Electrical or Computer Engineering, proficiency with VHDL/Verilog/SystemVerilog and verification methodologies, strong communication, and U.S. Person eligibility (ITAR).
VHDL, Verilog, SystemVerilog, UVM, VIP, PCIe, Ethernet
3mo
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ASIC Design Verification Engineer
Santa Clara, California, United States
$106k-$172k/yr OnsiteFull Time
3+ YOEBS in EE, CE, or CS; minimum 3 years ASIC verification; SystemVerilog/UVM; test plans, coverage, and debug; Python automation; strong collaboration.
SystemVerilog, UVM, Python, C++, Perl, UNIX Shell
2mo
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Principal Engineer, ASIC Design Verification
San Jose, California, United States
$190k-$240k/yr OnsiteFull Time
12+ YOEMS in Electrical or Computer Engineering; 12+ years ASIC/SoC verification experience; SystemVerilog and UVM expert; verification environment design; scripting for automation.
SystemVerilog, UVM, Scripting (Python, Perl, Tcl, Shell)
1mo
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ASIC/FPGA Verification Engineer III
Denver or Highlands Ranch or King of Prussia or Sunnyvale
$101k-$178k/yr OnsiteFull Time
3+ YOEB.S. in Electrical Engineering or equivalent, 3+ years professional ASIC/FPGA verification experience, SystemVerilog and UVM/OVM/VMM proficiency, HDL and scripting experience, ability to obtain/maintain DoD Secret clearance (US citizenship required).
SystemVerilog, Universal Verification Methodology (UVM), OVM, VMM, VHDL, Verilog, Linux, Perl, TCL, Python
1mo
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ASIC Formal Verification Engineer, TPU Compute
Sunnyvale, California, United States
$163k-$237k/yr OnsiteFull Time
8+ YOEBachelor's in Electrical/Computer Engineering or Computer Science; 8 years in silicon/ASIC/SoC design; experience with SystemVerilog Assertions and formal verification.
2mo
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Staff Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
6+ YOEBS in electrical engineering or computer science; 6-8 years verification; RTL debugging, scoreboarding, and code coverage; test plans and coverage definitions.
SystemVerilog, UVM, C, DDR, PCIe/NVMe, NAND
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