New York City • 50 milesRemote · Hybrid · Onsite · Field · All Environments
New York City • 50 milesRemote · Hybrid · Onsite · Field · All Environments
New York City • 50 milesRemote · Hybrid · Onsite · Field · All Environments
New York City • 50 milesRemote · Hybrid · Onsite · Field · All Environments
13 asic verification engineer jobs at 12 companies in New York City, NY
2w
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ASIC Engineer
New York City, New York, United States
$250k-$300k/yr OnsiteFull Time
4+ YOE4+ years RTL design and verification experience; ASIC design using Synopsys or Cadence flows; experience in front-end, back-end or verification; FPGA/ASIC familiarity; programming experience (Python, C++, Java, Haskell); willingness to learn OCaml.
Hardcaml, OCaml, Synopsys, Cadence, Python, C++, Java, Haskell
1mo
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Integrated Circuit Design Verification Engineer
Vancouver or Washington or California or New York City
$147k-$259k/yr OnsiteFull Time
10+ YOE10+ years of ASIC design verification experience, BSEE or MSEE (or equivalent), strong UVM/SystemVerilog skills, Siemens Questa experience, scripting (TCL/Make/Perl/Python/Shell), and excellent communication.
UVM, SystemVerilog, Siemens Questa, TCL, Make, Perl, Python, Shell, Linux
2mo
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Design Verification Engineering Lead - Silicon One
San Jose or New York City or New York or Washington or Illinois or United States or Canada
$211k-$305k/yr OnsiteFull Time
5+ YOEDegree plus extensive ASIC DV experience (Bachelors+12/Masters+8/PhD+5), recent Verilog/SystemVerilog/UVM experience, scripting (Perl or Python), ASIC verification, emulation and bring-up experience.
Verilog, SystemVerilog, UVM, Perl, Python, Linux, C, C++, Veloce, Palladium, Zebu, HAPS, Jasper Gold, Cursor, Codex, CoPilot, P4
1mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
2w
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Senior Engineer, Physical Design Engineering (ASIC)
Somerset County or Wilmington
$117k-$161k/yr OnsiteFull Time
5+ YOEExpertise in ASIC/SoC physical design, floorplanning, P&R, timing closure, physical verification, scripting (TCL/Python), and cross-functional collaboration; 5+ years experience preferred.
Cadence, TCL, Python
1w
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Hardware Engineer III
Gurgaon or New York City
HybridFull Time
3+ YOEBachelor's degree in electrical engineering or equivalent experience; 3–5 years in ASIC/FPGA development and verification; expertise in Verilog, SystemVerilog/VHDL, Xilinx tools, networking, Linux, Python, and C/C++.
Verilog, SystemVerilog, VHDL, Xilinx, cocotb, UVM, Linux, Shell scripting, Python, C, C++, FPGA, ASIC, Ethernet, PCIe
1mo
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Two Sigma Securities, Hardware Engineer
New York City, New York, United States
$165k-$300k/yr HybridFull Time
1+ YOEMinimum 1 year RTL design and verification experience, proficiency in SystemVerilog and Python, FPGA/ASIC knowledge, timing analysis, network protocol familiarity; C++ is a plus.
SystemVerilog, Python, FPGA, ASIC, C++
3w
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Principal Engineer - Design
Hauppauge, New York, United States
$75k-$232k/yr OnsiteFull Time
10+ YOEBachelor's in Electrical Engineering or equivalent,10+ years relevant experience,Verilog/System Verilog proficiency,experience with Ethernet/USB/PCIe and ASIC design/verification,strong problem solving and communication skills.
Verilog, System Verilog, Xilinx FPGA
2mo
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FPGA Engineer
Amsterdam or Chicago or London or New York City or Singapore
OnsiteFull Time
Professional FPGA/ASIC design and verification experience; SystemVerilog/Verilog/VHDL and C++; familiarity with EDA tools and scripting (TCL, Python, Bash); university degree in EE/CS/CE or related.
SystemVerilog, Verilog, VHDL, C++, TCL, Python, Bash, EDA
1mo
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
2mo
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Senior Engineer, Digital Design Engineering
Somerset, New Jersey, United States
$127k-$175k/yr HybridFull Time
2+ YOEMaster’s degree in Electrical/Electronic/Computer Engineering or related field; 2+ years in digital design/mixed-signal verification; experience with RTL, Verilog/SystemVerilog, and ASIC/FPGA design flows.
Verilog, SystemVerilog, Cadence, Synthesis, CDC, Verifications tools
4w
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FPGA Engineer - Control Systems
Princeton, New Jersey, United States
$150k-$235k/yr OnsiteFull Time
Experienced in FPGA/ASIC digital logic design and verification, RTL and low-latency firmware for multi-domain clock systems; familiarity with Xilinx/AMD RFSoC platforms preferred.
RTL, FPGAs, ASICs, Xilinx, AMD, RFSoC
1mo
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Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route