279 circuit jobs at 116 companies in San Jose, CA
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Photonics Circuit Designer
Palo Alto, California, United States
$120k-$145k/yr OnsiteFull Time
5+ YOEPhD in Electrical Engineering or Physics; 5+ years in integrated photonics; strong Python; photonic device/circuit design experience.
Python, Wolfram Language, Photonic design software
2w
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SRAM Circuit Design Engineer
Santa Clara, California, United States
OnsiteFull Time
Experienced in custom silicon circuit design, able to create novel SRAM/circuit solutions and influence CPU/GPU/SoC architectures; strong engineering fundamentals and innovation mindset.
3mo
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Senior Circuit Methodology Engineer
Santa Clara, California, United States
$168k-$311k/yr OnsiteFull Time
8+ YOEBachelors in EE/CE or equivalent, 8+ years in circuit design methodology, proficient in Python and Perl, experience with Cadence/Synopsys flows (Virtuoso/Custom Compiler), and familiarity with LSF and Slurm job schedulers.
Python, Perl, Cadence, Synopsys, Virtuoso, Custom Compiler, LSF, Slurm
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Senior NVM Circuit Designer
Palo Alto or Austin or United States
$120k-$225k/yr HybridFull Time
5+ YOEPh.D. or MS in EE or related,5–10+ years NVM memory design and tapeout experience,hands-on circuit simulation and silicon debugging,Python,Verilog-A,SystemVerilog RNM,SPICE and Cadence Virtuoso proficiency.
Verilog-A, System Verilog Real Number Modeling, Verilog, Python, SPICE, Cadence Virtuoso
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Principal SoC Circuit Architect
Mountain View or Sacramento
$143k-$275k/yr HybridFull Time
8+ YOEAdvanced degree or equivalent experience in electrical/computer engineering, 8+ years SoC circuit architecture experience, expertise in high-speed IO PHY, PLL/clocking, signal and power integrity, ability to pass security and export-control screenings.
2d
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Circuit Design Engineer III, Avionics
Sunnyvale, California, United States
$123k-$228k/yr OnsiteFull Time
3+ YOEBachelor's degree in electrical engineering or related field, 3+ years of experience designing digital or analog circuits and performing electronics analysis; U.S. citizenship required for DoD Secret clearance.
Zuken, PSPICE, Saber, SPICE, FPGA, Printed Wiring Board
3mo
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Senior Circuit Methodology Engineer
Santa Clara, California, United States
$168k-$311k/yr OnsiteFull Time
8+ YOEBSEE/BSCE or equivalent; mid-level Python and Perl; 8+ years circuit design methodology with Cadence/Synopsys; experience with job schedulers and compute farms (LSF/Slurm); strong debugging and collaboration skills.
Cadence, Synopsys, Virtuoso, Custom Compiler, LSF, Slurm, Python, Perl
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Memory Circuit Design Engineer
Hillsboro or Santa Clara or Austin or Phoenix
$122k-$232k/yr HybridFull Time
4+ YOEMaster's in EE/CE + 4+ years' experience or PhD; experience designing/characterizing memory circuits (SRAM/ROM/Register Files), PPA optimization, custom digital design, simulation, layout, verification, and knowledge of EDA tools.
EDA tools
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Staff Engineer, SRAM Circuit Design
San Jose, California, United States
$163k-$253k/yr OnsiteFull Time
8+ YOE8+ years experience in SRAM or memory circuit design, strong EE background, expertise with advanced nodes, device physics, Cadence/Spectre/HSPICE simulation, scripting (Python/Perl/TCL), and experience with layout/DFM and silicon bring-up.
HSPICE, finesim, Cadence Spectre, Cadence Virtuoso, Python, Perl, TCL
3w
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Custom Circuit Design (Sr. Staff / Principal)
Bengaluru or Santa Clara
$125k-$500k/yr OnsiteFull Time
10+ YOE10+ years custom digital/transistor-level CMOS circuit design experience; expertise in standard cell and low-power design; proficiency with HSPICE/PrimeSim XA/Spectre and StarRC/Quantus; reliability and variation-aware verification; technical leadership.
Cadence Virtuoso, StarRC, Quantus, HSPICE, PrimeSim XA, Spectre, Solido, Spectre FMC, Liberate, PrimeLib, Python, Tcl, Perl
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Analog Circuit Design Engineer
San Jose, California, United States
$149k-$216k/yr OnsiteFull Time
10+ YOEBSEE/MSEE/PhD in Electrical Engineering or equivalent with 10+ years analog/mixed-signal design experience; experience with amplifiers, ADCs, regulators, SerDes; proficiency with Virtuoso, Spice, StarRC, Totem; Verilog and UPF knowledge.
Virtuoso, Spice, StarRC, Totem, Verilog, UPF, ICCT, IBIS
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Sr High Speed Mixed Signal Circuit Design Eng
San Jose, California, United States
$119k-$171k/yr OnsiteFull Time
3+ YOEDesign and bring to production high-speed analog/mixed-signal circuits (ADCs, DACs, PLLs) in advanced CMOS; 3+ years experience; familiarity with CAD tools; Verilog-A/AMS modeling; strong circuit analysis and layout understanding.
Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, Totem EM/IR, Verilog-A, Verilog-AMS, Matlab
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Lead Photonics Integrated Circuit Engineer
San Francisco or United States
HybridFull Time
PhD in physics/EE with deep expertise in quantum photonics, semiconductor process integration, PIC design/tape-out, modelling and characterization; experience with Cadence Virtuoso, verification flows and photonic simulation tools.
C++, Python, SKILL, TCL, HDL, MATLAB, Lumerical, COMSOL, MEEP, Cadence Virtuoso, Calibre, Hercules, ICV, Dracula, Primeyield, Verilog-A
1mo
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Integrated Circuit - Packaging Architect Engineer
San Jose, California, United States
$183k-$314k/yr HybridFull Time
Proven track record in semiconductor technology development and leadership; define package architecture, DFM/DFY and yield roadmaps; collaborate with product architects and manufacturing partners; strong communication skills; BS/MS/PhD in related fields.
2w
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Photonic Integrated Circuit (PIC) Researcher
Santa Clara, California, United States
$164k-$274k/yr OnsiteFull Time
Ph.D. in photonics/EE/optics/physics, strong PIC simulation, design, layout and characterization experience, proficiency with PIC probing, and excellent written and verbal English communication.
RSoft, Lumerical, Tidy3D, IPKISS, KLayout, ADS, INTERCONNECT, VPI, Python
2w
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Photonic Integrated Circuit (PIC) Researcher
Santa Clara, California, United States
$164k-$274k/yr OnsiteFull Time
Completed PhD in photonics/EE/optics/physics, demonstrated integrated photonics research, PIC simulation and layout experience, hands-on PIC characterization, strong written and verbal English, and collaborative teamwork skills.
RSoft, Lumerical, Tidy3D, IPKISS, KLayout, ADS, INTERCONNECT, VPI, Python
2w
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Principal Engineer, SRAM Compiler & Circuit Design (7820)
San Jose, California, United States
$140k-$225k/yr HybridFull Time
3+ YOEPhD+3yrs or MS+8yrs or BS+12yrs industry experience; deep SRAM/compiler expertise; proficiency with Cadence and Synopsys toolflows; scripting in Perl, Shell, TCL, Python; sub-7nm process experience.
Cadence, Synopsys, Virtuoso, Spectre, HSPICE, FineSim, Perl, Shell, TCL, Python
4d
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Technical Lead, Custom Digital Circuit Design, Mixed Signal
Sunnyvale or Haifa or Tel Aviv
$240k-$333k/yr OnsiteFull Time
12+ YOEBachelor’s degree or equivalent practical experience and 12 years in physical design, custom digital circuit design, or custom layout; experience delivering GDS for advanced nodes required.
GDS, AI, TPU, Tensor Processing Unit, AI/ML, Analog and Mixed-Signal (AMS), GAA, Gate-All-Around, Design for Manufacturing (DFM)
2mo
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Director - AI Research and Engineering Efficiency (Circuit Platform)
San Jose, California, United States
$292k-$369k/yr HybridFull Time
15+ YOEDirector-level role leading AI research and engineering efficiency for Circuit Platform; 15+ years software/AI systems experience; enterprise-scale LLM/agentic AI expertise; strong leadership and architecture skills.
LLM platforms, model-serving, routing, caching, quantization, distillation, prompt optimization, inference serving
2w
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Senior Integrated Circuit Wafer Probe Hardware Design & Validation Engineer (Probe Specialist)
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOE12+ years probe card and probe hardware experience; degree in EE/ME/Materials; expertise with VNAs, TDR, oscilloscopes, wafer probers, SI/PI, CAD and FEA; supplier and failure-analysis experience.
Vector Network Analyzers (VNAs), Time-Domain Reflectometry (TDR), oscilloscopes, wafer prober, Advantest, Teradyne, SolidWorks, Autodesk Inventor, Creo, FEA, Python, MATLAB
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