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Senior CPU Design Verification Engineer
Austin or Phoenix
$142k-$200k/yr HybridFull Time
4+ YOE4+ years in design verification; SystemVerilog/UVM; pre-silicon CPU/SoC verification; strong debugging; Bachelor's or Master in Electrical or Computer Engineering.
SystemVerilog, UVM, EDA tools, Python, Linux
2w
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CPU Design Methodology Engineer
Hillsboro or Austin or Santa Clara or United States
$136k-$265k/yr HybridFull Time
5+ YOEMasters in Computer/Electrical Engineering or equivalent experience,5+ years chip/SOC design experience,RTL (Verilog),UVM/System Verilog,design automation,Perl/Python skills,analytical and interpersonal skills.
Verilog, UVM, System Verilog, Perl, Python
2d
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CPU Core Design Verification Engineer
Austin, Texas, United States
$102k-$154k/yr HybridFull Time
Experience verifying CPU microarchitecture using C++ and SystemVerilog, strong computer-architecture fundamentals, RTL/Verilog knowledge, familiarity with verification tools (VCS, Cadence, Mentor), scripting (Python/Perl), and Bachelors/Masters in computer or electrical engineering.
C++, SystemVerilog, Verilog, VCS, Cadence, Mentor Graphics, Python, Perl
1mo
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Senior CPU Power Delivery Engineer
Austin, Texas, United States
$152k-$255k/yr OnsiteFull Time
5+ YOEBS/MS/PhD in electrical engineering, 5+ years power delivery/power integrity experience for digital ICs, PDN simulation tool experience, CPU power knowledge, advanced-node physical design experience.
Apache Redhawk, Voltus, SIwave, oscilloscope, VNA, PDN analyzer
1mo
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Staff RTL Design Engineer - CPU LS/PF/MMU
Santa Clara or Austin
$179k-$219k/yr OnsiteFull Time
3+ YOEBS/MS in CS/CE/EE or equivalent, 3+ years design experience, CPU RTL design experience, proficiency in Verilog/System Verilog/VHDL, strong software engineering (OOP, functional, TDD), verification skills (SVA, coverage).
Chisel, FIRRTL, Verilog, System Verilog, VHDL, Scala, Bluespec, RISC-V, Git/Github, Jira, Confluence, SVA
2mo
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Sr. Engineer, CPU RTL Design
Austin or Santa Clara
$100k-$500k/yr HybridFull Time
Experience in CPU microarchitecture, RTL coding (Verilog/VHDL), and cross-functional collaboration.
Verilog, VHDL, Simulation Tools, Synthesis Tools, Power Analysis Tools
1d
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SRAM Circuit Design Engineer
Austin, Texas, United States
OnsiteFull Time
Experienced in silicon/circuit design and engineering fundamentals to contribute to CPU/GPU/SoC/Neural Engine designs and bring products to market.
1mo
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Senior/Staff Design Engineer
Santa Clara or Richardson or Austin
$69k-$202k/yr OnsiteFull Time
2+ YOEBachelor's (3–7 yrs) or Master's (2–5 yrs); knowledge of CPU microarchitecture, System Verilog/Verilog/VHDL, simulators, timing/power; scripting in Perl or Python; experience with RISC-V/ARM/MIPS preferred.
System Verilog, Verilog, VHDL, Perl, Python, RISC-V, ARM, MIPS
2w
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Senior GPU Design Verification Engineer (GCDV)
Austin or San Jose
$124k-$208k/yr OnsiteFull Time
2+ YOE2+ years verification experience with GPU/CPU/semiconductor designs, SystemVerilog/C++/Python skills, understanding of computer architecture and graphics pipelines, strong communication and debugging skills.
SystemVerilog, C++, python
3w
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BIOS Senior/Lead Software Engineer
Austin, Texas, United States
OnsiteFull Time
6+ YOEExpert C programming and low-level firmware/BIOS/boot loader experience; CPU bring-up experience; familiarity with Linux kernel, x86/ARM architectures; strong software design, debugging, and communication skills.
C, C++, Python, Linux Kernel, x86, ARM, EOS
1mo
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Principal Heterogeneous Systems Architect
Austin, Texas, United States
HybridFull Time
10+ YOEBS in EE/CE/CS (MS/PhD preferred), 10+ years in system/platform/compute architecture, deep knowledge of heterogeneous computing (CPUs, GPUs, FPGAs, accelerators), HW/SW co-design experience, programming in C/C++, Python, CUDA/OpenCL/SYCL or HDL, US work authorization required.
C/C++, Python, CUDA, OpenCL, SYCL, Verilog, VHDL