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CPU Design Verification Engineer
Austin, Texas, United States
OnsiteFull Time
3+ YOEBS plus 3+ years in CPU architecture/verification; experience in digital logic design, chip architecture, and languages like C/C++/SystemVerilog.
C, C++, SystemVerilog, Assembly
1mo
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Staff CPU Processor Design Engineer
San Diego, California, United States
$148k-$223k/yr RemoteFull Time
Lead block-level verification for complex CPU designs using simulation, formal, and emulation methods; develop testplans, verification environments, assertions, and scripts (Python/Perl); collaborate with microarchitecture and bring-up teams.
Assertion Based Verification, Formal Verification, Emulation, RTL, FPGA, Python, Perl
1w
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CPU Design Methodology Engineer
Hillsboro or Austin or Santa Clara or United States
$136k-$265k/yr HybridFull Time
5+ YOEMasters in Computer/Electrical Engineering or equivalent experience,5+ years chip/SOC design experience,RTL (Verilog),UVM/System Verilog,design automation,Perl/Python skills,analytical and interpersonal skills.
Verilog, UVM, System Verilog, Perl, Python
1mo
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CPU Physical Design Engineer
Austin, Texas, United States
$106k-$200k/yr OnsiteFull Time
2+ YOEBachelor’s or Master’s in Computer/Electrical Engineering with relevant experience; strong background in digital synthesis, physical design flows, and verification.
Synopsys, Cadence, Synthesis, Place and Route, Static Timing Analysis, DRC/LVS, TCL scripting
1d
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Senior CPU RTL Design Engineer
Mountain View, California, United States
$163k-$237k/yr OnsiteFull Time
8+ YOEBachelor's degree or equivalent,8+ years implementing CPU cache subsystems,RTL/System Verilog experience,and familiarity with lint and UPF; strong microarchitecture and collaboration skills.
System Verilog, Lint, UPF, ARM Instruction Set Architecture
2w
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CPU Core RTL Design Engineer
Austin, Texas, United States
HybridFull Time
Design and implement CPU core RTL, contribute to microarchitecture, collaborate with verification and physical design, and debug pre/post-silicon issues; Bachelor’s+ in EE/CE preferred.
Verilog, SystemVerilog, Python, Tcl
3mo
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Senior RTL Design Engineer - CPU Frontend
Santa Clara, California, United States
$159k-$194k/yr OnsiteFull Time
3+ YOE3+ years of RTL design experience; Verilog/SystemVerilog/VHDL; CPU RTL design; Chisel/Scala experience a plus; strong software engineering skills.
Verilog, SystemVerilog, VHDL, Chisel, FIRRTL, Scala, Bluespec, Git, Jira, Confluence
1w
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CPU Design Methodology Engineer
Hillsboro or Austin or Santa Clara or Arizona
$136k-$265k/yr OnsiteFull Time
5+ YOEMasters in Computer or Electrical Engineering or equivalent,5+ years chip/SOC design experience,RTL/verification and design automation expertise,proficient in scripting (Perl/Python),strong analytical and interpersonal skills.
Verilog, UVM, System Verilog, Perl, Python
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Senior CPU Power Delivery Engineer
Austin, Texas, United States
$152k-$255k/yr OnsiteFull Time
5+ YOEBS/MS/PhD in electrical engineering, 5+ years power delivery/power integrity experience for digital ICs, PDN simulation tool experience, CPU power knowledge, advanced-node physical design experience.
Apache Redhawk, Voltus, SIwave, oscilloscope, VNA, PDN analyzer
2mo
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Sr. Engineer, CPU RTL Design
Austin or Santa Clara
$100k-$500k/yr HybridFull Time
Experience in CPU microarchitecture, RTL coding (Verilog/VHDL), and cross-functional collaboration.
Verilog, VHDL, Simulation Tools, Synthesis Tools, Power Analysis Tools
2mo
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Principal Design Verification Engineer
Austin or Texas or Santa Clara or Malta
$153k-$290k/yr OnsiteFull Time
8+ YOEBachelor's in engineering, 8+ years design verification (CPU/SoC) experience, hands-on SystemVerilog/UVM and constrained-random verification, scripting in Python/Perl/Shell, familiarity with CPU architectures and cache/coherency concepts.
SystemVerilog, UVM, C, Assembly, Python, Perl, Shell
1mo
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Design Lead - BIOS, Test/Interface/Uc Board Design, CPU (113908)
United States
OnsiteFull Time
Expertise in BIOS, test/interface/uC board, and CPU design; strong hardware and circuit design knowledge; experience with BIOS development tools, testing, and debugging; familiarity with microcontrollers, microprocessors, and SoC architectures; mentoring experience.
1mo
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Senior Design and Analysis Engineer
Berkeley, Missouri, United States
$137k-$185k/yr OnsiteFull Time
9+ YOEBachelor's degree in engineering or related field, 9+ years of related experience, ability to obtain U.S. Secret clearance (U.S. citizenship required). Experience with OMS, MBSE, hardware design, SOSA/VPX, FPGAs/GPUs/CPUs preferred.
Open Mission Systems (OMS), Model Based System Engineering (MBSE), SOSA, VPX, XMC, FPGA, GPU, CPU, Cross Domain Solutions
2mo
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Principal Design Verification Engineer
Austin or Santa Clara
$153k-$290k/yr OnsiteFull Time
8+ YOE8+ years in design verification of CPU/SoC, SystemVerilog/UVM, constrained random verification, and scripting.
SystemVerilog, UVM, Python, Perl, Shell
1mo
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Senior Design Verification Engineer
San Jose, California, United States
$168k-$336k/yr OnsiteFull Time
5+ YOE5+ years UVM/System Verilog design verification experience, BS in EE/CS required (MS preferred), GenAI and agentic MCP experience, ASIC simulation and SoC/CPU emulation expertise, System Verilog/System C/C++ skills, test plan and coverage closure experience.
GenAI, agentic MCP, UVM, System Verilog, System C, C++
1mo
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Electronics Hardware Design Engineer 2
Cambridge, Massachusetts, United States
$75k-$156k/yr OnsiteFull Time
3+ YOEBachelor's in electrical/electronic engineering (Master's preferred), 3+ years engineering experience, PCB and analog/digital design, FPGA/microprocessor knowledge, prototype build/test, programming ability, and ability to obtain a government security clearance.
printed circuit boards (PCBs), PCBs, microprocessors, processors, FGPAs, FPGAs, systems on a chip (SOCs), microcontrollers
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Senior Design Verification Engineer
San Jose, California, United States
$168k-$336k/yr OnsiteFull Time
5+ YOE5+ years UVM/SystemVerilog verification, Bachelor’s in EE or CS, GenAI and agentic MCP experience, ASIC simulation and SoC/CPU emulation experience, SystemC/C++ and scripting skills, test plan and coverage closure experience.
UVM, SystemVerilog, GenAI, agentic MCP, ASIC simulation tools, SystemC, C++
1mo
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Design Verification Engineer IV
San Jose, California, United States
$112k-$176k/yr OnsiteFull Time
6+ YOEExpertise in SystemVerilog/UVM, AXI/PCIe/Ethernet/NOC/UCIe protocols, CPU architectures (ARM, RISC-V) and C/C++; 6–8+ years verification experience; formal verification and scripting experience; ability to architect SoC verification environments.
SystemVerilog (SV), UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, C++
1w
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Senior GPU Design Verification Engineer (GCDV)
Austin or San Jose
$124k-$208k/yr OnsiteFull Time
2+ YOE2+ years verification experience with GPU/CPU/semiconductor designs, SystemVerilog/C++/Python skills, understanding of computer architecture and graphics pipelines, strong communication and debugging skills.
SystemVerilog, C++, python
1w
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Staff Engineer, System Design Engineering
Milpitas, California, United States
$104k-$172k/yr HybridFull Time
2+ YOEBachelor’s in CS/CE with 5+ years or Master’s with 2+ years; experience in AI infrastructure benchmarking, GPU/CPU architectures, performance profiling, scripting (Shell, Python, C/C++), and OS (Linux, Windows, VMware).
Windows, Linux, VMware, Shell, Python, C, C++, NVLink, NVSwitch, PCIe, NVMe
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