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Senior CPU Design Verification Engineer
Austin or Phoenix
$142k-$200k/yr HybridFull Time
4+ YOE4+ years in design verification; SystemVerilog/UVM; pre-silicon CPU/SoC verification; strong debugging; Bachelor's or Master in Electrical or Computer Engineering.
SystemVerilog, UVM, EDA tools, Python, Linux
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CPU RTL Design Engineer
Austin or Phoenix
$142k-$269k/yr HybridFull Time
5+ YOEDegree in EE/CE/CS with significant experience (typical 5+ yrs); 7+ yrs RTL design with Verilog/V2K/SystemVerilog; low-power, CDC, static timing, UPF knowledge; scripting with TCL/Perl/Python; strong communication.
Verilog, V2K, System Verilog, TCL, Perl, Python, UPF, x86 assembly
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Senior CPU RTL Design Engineer – Power Management
Austin or Phoenix
$164k-$269k/yr HybridFull Time
7+ YOEBachelor's (9+ years) or Master's (7+ years) in ECE/CE/CS. Experience in low-power CPU/SoC RTL design, power management (DVFS, power states), RTL development (Verilog/SystemVerilog), debug and system-level design. Preferred: CDC, static timing analysis, UPF, lint.
SystemVerilog, Verilog, x86 assembly, CDC, UPF, static timing analysis, lint