2mo
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Director, Design Verification
San Jose, California, United States
$219k-$351k/yr OnsiteFull Time
15+ YOEBE/MS in Computer/Electrical Engineering or Computer Science; 15+ years ASIC verification; leadership in verification; multiple tape-outs; UVM, C++, SystemVerilog; strong communication and collaborative skills.
UVM, C++, SystemVerilog, verification tools
3mo
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Design Verification Engineer
Austin, Texas, United States
OnsiteFull Time
10+ YOEBS with 10+ years in digital verification; SystemVerilog, UVM, Python/Perl; SOC/IP verification experience; strong communication.
SystemVerilog, UVM, Python, Perl, C/C++, Digital design, Scripting
2mo
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Director, Design Verification
Santa Clara, California, United States
$195k-$292k/yr OnsiteFull Time
20+ YOELead design verification for ASICs; 20+ years exp or 15+ with advanced degree; strong leadership and communication.
2mo
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Design Verification Architect
San Jose or United States
$150k-$300k/yr HybridFull Time
12+ YOEBachelor's/Master's in EE/CE, 12+ years design verification experience for large SoCs, expertise in SystemVerilog, UVM, Portable Stimulus (PSS), coverage-driven and assertion-based verification, and strong architecture and debugging skills.
SystemVerilog, UVM, Portable Stimulus (PSS), PCIe, DDR, Ethernet, CXL, UCIe
3d
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Design Verification Lead
San Jose, California, United States
$200k-$300k/yr HybridFull Time
10+ YOEMinimum 10 years UVM design verification experience; Bachelor's or Master's in EE/CE/CS or related; expertise in SystemVerilog/Verilog, UVM, high-speed protocol verification (PCIe, CXL, Ethernet); scripting with Python/Perl; technical leadership and mentoring.
UVM, SystemVerilog, Verilog, PCIe, CXL, Ethernet, Python, Perl, HLS
2mo
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Principal Design Verification Engineer
Austin or Santa Clara
$153k-$290k/yr OnsiteFull Time
8+ YOE8+ years in design verification of CPU/SoC, SystemVerilog/UVM, constrained random verification, and scripting.
SystemVerilog, UVM, Python, Perl, Shell
3mo
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Design Verification Engineer - SoC
San Jose, California, United States
$150k-$275k/yr OnsiteFull Time
Design verification for ASIC/SoC; SystemVerilog and Python; performance modeling; test benches and verification infrastructure.
SystemVerilog, Python
1mo
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Design Verification Engineer
Sunnyvale, California, United States
$190k-$230k/yr OnsiteFull Time
3+ YOE3+ years design verification experience; deep knowledge of SystemVerilog, DPI, UVM; strong programming (object-oriented) skills; experience with testbenches, simulation, emulation, and silicon bring-up.
SystemVerilog, DPI, UVM, Python, Perl
4d
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Design Verification Manager
Sunnyvale, California, United States
$174k-$353k/yr OnsiteFull Time
10+ YOE5+ Mgmt10+ years pre-silicon ASIC/SoC verification experience, 5+ years engineering management, expert SystemVerilog and UVM, formal verification, emulation platforms, SoC verification strategy and leadership.
SystemVerilog, Universal Verification Methodology (UVM), Palladium, Zebu, Veloce, Artificial Intelligence, Machine Learning, PCIe, CXL, HBM3, NVLink
1mo
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Design Verification Engineer
Lakeway or Austin
OnsiteFull Time
7+ YOEBSc/MSc in engineering or CS, 7+ years verification experience, expert SystemVerilog/UVM development, protocol verification (AXI, DDRx, PCIe, USBx), verification planning, and ability to travel; eligible to work in the US.
SystemVerilog, UVM, Specman/e, C, C++, Python, Perl
1w
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience with SystemVerilog, UVM, ABV, and scripting; production verification and silicon bring-up experience preferred.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
1mo
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MTS, DEG Design Verification
Boise, Idaho, United States
OnsiteFull Time
Bachelor's in EE/CE, strong DRAM circuit design/verification expertise, experience with HSPICE, Finesim, Verilog/SystemVerilog, Python; leadership, mentoring, CMOS fundamentals, and verification methodology skills.
HSPICE, Finesim, Verilog, SystemVerilog, UVM, Python, ClaudeCode, EDA
1mo
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Design Verification Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's in EE/electronic engineering or CS required; 12+ years experience; strong System Verilog, UVM/OVM, RTL, C/C++, Perl, SystemC skills; ASIC design verification, debugging, and coverage experience; US work authorization required.
System Verilog, UVM, OVM, RTL, C/C++, Perl, SystemC, Emulators, FPGA
1mo
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ASICS Design Verification Engineer
San Diego, California, United States
$116k-$173k/yr OnsiteFull Time
2+ YOEBachelor's degree and 2+ years ASIC design/verification experience. Experience with SystemVerilog-UVM, testbench and coverage development, assertion/formal verification, UPF, scripting (Perl/Python), and AMBA protocols.
SystemVerilog, UVM, Verilog, VHDL, C, C++, Perl, Python, AMBA Bus protocol (AXI/AHB/APB), UPF, Assertion Based Formal Verification
4d
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Design Verification Engineer
Aliso Viejo or San Jose or Córdoba or Toronto
OnsiteFull Time
3+ YOEBachelors in EE/CE/CS,3+ years verification experience, SystemVerilog/UVM, coverage-driven verification, C/C++ and scripting (Python,Tcl,Perl),test planning and debug skills.
SystemVerilog, UVM, C, C++, Python, Tcl, Perl
4d
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Design Verification Manager
Sunnyvale, California, United States
$174k-$353k/yr OnsiteFull Time
10+ YOE5+ Mgmt10+ years pre-silicon ASIC/SoC verification experience, 5+ years engineering management, expert SystemVerilog and UVM, formal verification and emulation experience, bachelor\u0002s in EE/CS or related.
SystemVerilog, Universal Verification Methodology (UVM), Palladium, Zebu, Veloce
4d
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Design Verification Manager
Sunnyvale, California, United States
$174k-$353k/yr OnsiteFull Time
10+ YOE5+ Mgmt10+ years pre-silicon ASIC/SoC verification experience, 5+ years engineering management, expert SystemVerilog/UVM, formal verification, emulation experience, BS in EE/CS/CE or related.
SystemVerilog, Universal Verification Methodology (UVM), Palladium, Zebu, Veloce
2mo
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Principal Design Verification Engineer
Austin or Texas or Santa Clara or Malta
$153k-$290k/yr OnsiteFull Time
8+ YOEBachelor's in engineering, 8+ years design verification (CPU/SoC) experience, hands-on SystemVerilog/UVM and constrained-random verification, scripting in Python/Perl/Shell, familiarity with CPU architectures and cache/coherency concepts.
SystemVerilog, UVM, C, Assembly, Python, Perl, Shell
2mo
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MTS, DEG Design Verification
Boise, Idaho, United States
OnsiteFull Time
Bachelor's in Electrical/Computer Engineering or related field; DRAM design/verification expertise; experience with HSPICE, Verilog/SystemVerilog; CMOS fundamentals; leadership and collaboration.
HSPICE, Finesim, Verilog, SystemVerilog, UVM, Python
1mo
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Senior Design Verification Engineer
Austin, Texas, United States
OnsiteFull Time
4+ YOEBachelor's in EE/CE/CS required, 4+ years IP/SoC design or verification experience, Verilog/SystemVerilog/UVM skills, SVA and verification (test planning, simulation, debug), familiarity with Python, C/C++, Perl, TCL and AI/ML tools; ARM AMBA knowledge a plus.
Verilog, SystemVerilog, UVM, System Verilog Assertion (SVA), Python, C/C++, Perl, TCL, Makefiles, AI/ML tools, ARM AMBA, RTL
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