Battle Ground • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Battle Ground • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Battle Ground • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Battle Ground • 50 milesRemote · Hybrid · Onsite · Field · All Environments
41 design verification engineer jobs at 10 companies in Battle Ground, WA
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Design Verification Engineer
Raleigh or Hillsboro or Austin or Mountain View or Redmond
$102k-$202k/yr HybridFull Time, Contract
1+ YOEMaster's+1 or Bachelor's+2 years technical engineering experience (or equivalent); verification of silicon/IP using UVM/System Verilog/Formal; Python scripting; knowledge of CHI/AMBA/PCIe/CXL preferred; pass Microsoft Cloud Background Check and export-control screening.
UVM, Formal, System Verilog, Python
2mo
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SoC Physical Design Verification Engineer
Beaverton, Oregon, United States
OnsiteFull Time
Experience with physical verification of system-on-chip (SoC) designs and contributing to the design and manufacture of high-performance, power-efficient processors.
3mo
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Senior Engineer Design Verification Engineering
Beaverton, Oregon, United States
$119k-$163k/yr HybridFull Time
2+ YOEMaster's in CS/CE/EE or related field with 2 years in design verification; or Bachelor's with 4 years, plus strong scripting and verification experience.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Perl, Python, scripting
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Integrated Circuit Design Verification Engineer
Vancouver, Washington, United States
$173k-$259k/yr OnsiteFull Time
10+ YOE10+ years ASIC design verification experience; strong UVM/SystemVerilog skills; Siemens Questa; develop UVM/assertion testbenches, functional and code coverage, scripting/automation in Linux.
UVM, SystemVerilog, Siemens Questa, TCL, Make, Perl, Python, Shell, Linux
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Mixed Signal Design Verification Engineer
Hillsboro, Oregon, United States
$142k-$200k/yr HybridFull Time
2+ YOEBachelor's in EE/CE/CS with 3+ years or Master's with 2+ years; digital logic and VHDL/Verilog/System Verilog experience; testbench development (OVM/UVM); strong debug skills.
VHDL, Verilog, System Verilog, OVM, UVM
2w
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Design Verifciation Principal Engineer
Hillsboro, Oregon, United States
$127k-$237k/yr HybridFull Time
10+ YOEBachelor's in EE/CS, 10+ years in design verification, SystemVerilog/Verilog RTL fluency, HDL testbench experience, DDR familiarity preferred; Python and TCL scripting experience preferred.
System Verilog, Verilog, Python, TCL
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CPU Design Methodology Engineer
Hillsboro or Austin or Santa Clara or Arizona
$136k-$265k/yr OnsiteFull Time
5+ YOEMasters in Computer or Electrical Engineering or equivalent,5+ years chip/SOC design experience,RTL/verification and design automation expertise,proficient in scripting (Perl/Python),strong analytical and interpersonal skills.
Verilog, UVM, System Verilog, Perl, Python
1d
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CPU Design Methodology Engineer
Hillsboro or Austin or Arizona or Santa Clara
$168k-$311k/yr OnsiteFull Time
8+ YOEMaster's in computer or electrical engineering or equivalent experience; 8+ years in chip design focused on SoC integration and design automation; RTL, verification, scripting, synthesis, and physical design experience.
Verilog, Universal Verification Methodology (UVM), SystemVerilog, Perl, Python
2w
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Analog ASIC Design Engineer
Boulder or Louisville or Beaverton
HybridFull Time
5+ YOEBSEE or MSEE in EE, 5+ years analog/mixed‑signal IC design experience, ASIC design and verification tool proficiency, RF and layout experience, lab characterization, strong communication and collaboration skills.
Ansys HFSS, Cadence EMX
2mo
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Senior Applications Engineer - Emulation
Austin or San Diego or Costa Mesa or Wilsonville
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/emulation and prototyping of electronics chips and systems; BS or MS in EE, CE, CS or related fields.
Emulation platforms (Veloce, Palladium, Zebu), SystemVerilog, Verilog, VHDL, SystemC, C, C++, Perl, Python, XML, JSON
3w
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Project Manager
Austin or Hillsboro or Boise
$115k-$140k/yr HybridFull Time
Project manager for design-build advanced technology projects; bachelor's in engineering preferred; PMP desired; experience with Deltek Vantagepoint, Microsoft Project or Primavera P6; ability to perform field verifications and lead cross-cultural teams.
Deltek Vantagepoint, Microsoft Project, Primavera P6, vibe-coding platforms, AI Large Language Models
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