24 design verification engineer jobs at 20 companies in Dunellen, NJ
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Senior Design Verification Engineer
Tempe or Independence or Arizona or Ohio or San Jose or New York City
$142k-$224k/yr HybridFull Time
8+ YOE8+ years design verification experience with UVM and testbench development; Bachelor's in EE/CE or related; experience with Questa/Xcelium/VCS; AI/agentic DV experience preferred; US citizenship and ability to obtain Secret clearance; travel up to 10%.
UVM, SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
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Integrated Circuit Design Verification Engineer
Vancouver or Washington or California or New York City
$147k-$259k/yr OnsiteFull Time
10+ YOE10+ years of ASIC design verification experience, BSEE or MSEE (or equivalent), strong UVM/SystemVerilog skills, Siemens Questa experience, scripting (TCL/Make/Perl/Python/Shell), and excellent communication.
UVM, SystemVerilog, Siemens Questa, TCL, Make, Perl, Python, Shell, Linux
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
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Design Verification Engineering Lead - Silicon One
San Jose or New York City or New York or Washington or Illinois or United States or Canada
$211k-$305k/yr OnsiteFull Time
5+ YOEDegree plus extensive ASIC DV experience (Bachelors+12/Masters+8/PhD+5), recent Verilog/SystemVerilog/UVM experience, scripting (Perl or Python), ASIC verification, emulation and bring-up experience.
Verilog, SystemVerilog, UVM, Perl, Python, Linux, C, C++, Veloce, Palladium, Zebu, HAPS, Jasper Gold, Cursor, Codex, CoPilot, P4
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2027 Masters Hardware Design Verification Engineering Intern/Co-op
Austin or Boxborough or Fort Collins or Longmont or Fishkill or Rochester or Secaucus
$80k-$120k/yr HybridInternship, Temporary
Currently enrolled in a U.S. bachelor's program in electrical or computer engineering or related field; knowledge of programming, hardware verification, digital systems, and lab equipment preferred.
C++, Python, C, Perl, Shell, UVM, Verilog, SystemVerilog, MySQL, PHP, Linux, Unix, Windows, FSM, HDL, Oscilloscopes, Voltmeters, Logic analyzers, Multimeters
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Mechanical Design Engineer
Madison, New Jersey, United States
HybridFull Time
2+ YOEBachelor's in Mechanical Engineering, 2+ years mechanical design experience, proficiency in CAD (SolidWorks preferred), experience with design verification/testing, and ability to work in regulated medical device environments.
CAD, SolidWorks
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
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Senior Engineer, Digital Design Engineering
Somerset, New Jersey, United States
$127k-$175k/yr HybridFull Time
2+ YOEMaster’s degree in Electrical/Electronic/Computer Engineering or related field; 2+ years in digital design/mixed-signal verification; experience with RTL, Verilog/SystemVerilog, and ASIC/FPGA design flows.
Verilog, SystemVerilog, Cadence, Synthesis, CDC, Verifications tools
2d
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Quantum Systems Digital Design Engineer II
Redmond or California or New York City
$102k-$202k/yr OnsiteFull Time
1+ YOEMaster's in Physics or Electrical/Computer Engineering plus 1+ year experience, or bachelor's plus 2+ years. Requires FPGA design, Verilog/SystemVerilog, high-speed protocols, verification, timing closure, and security screening.
Verilog, SystemVerilog, VHDL, AXI4, AXI-Stream, JESD204, Aurora, Ethernet, UDP, PCIe, SERDES, MMCM, PLL, async FIFOs, ILA, ChipScope, Vivado, Vitis, Quartus, Prime, Tcl, Python, Git, Azure DevOps, UVM, RFSoC, gRPC, REST, HLS, C++, Windows, Linux, VS Code, GitHub
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Sr. Analog IC Design Engineer - IVR Architecture Team (Remote)
New York, New York, United States
$135k-$170k/yr HybridFull Time
MSEE with analog design experience; strong control theory, switching converter, CMOS analog, custom IC flows; experience with high-frequency IVR design, verification, and bench validation; proficiency in listed EDA tools and languages.
Cadence Virtuoso, LVS, DRC, SPICE, parasitic extraction, electromagnetics simulators, Verilog, Verilog-AMS, Python, Perl, Tcl, Cadence Skill, MATLAB
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Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
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Lead Hardware Engineer
Horsham, Pennsylvania, United States
$125k-$150k/yr OnsiteFull Time
2+ YOEAdvanced degree in EE/Computer Engineering, 2+ years engineering experience. Proficient in analog/digital/RF design, PCB layout, schematic capture, design verification, and technical communication.
CST 3D RF simulation software, Agile
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Project Engineer
Audubon, Pennsylvania, United States
OnsiteFull Time
3+ YOEBachelor's in Mechanical/Bio/Biomedical Engineering; 3+ years in mechanical design (medical devices); CAD (CREO/SolidWorks); design verification/validation; regulatory support; strong collaboration.
CREO, SolidWorks, Microsoft Excel, PowerPoint, Project
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Engineer,Quality
Turtle Creek or Edison
OnsiteFull Time
Bachelor's in engineering required; quality engineering or new product development experience preferred. Responsibilities include root cause analysis, FMEA, verification/validation testing, supplier qualification, audits, and design control documentation.
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ASIC Engineer
New York City, New York, United States
$250k-$300k/yr OnsiteFull Time
4+ YOE4+ years RTL design and verification experience; ASIC design using Synopsys or Cadence flows; experience in front-end, back-end or verification; FPGA/ASIC familiarity; programming experience (Python, C++, Java, Haskell); willingness to learn OCaml.
Hardcaml, OCaml, Synopsys, Cadence, Python, C++, Java, Haskell
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Project Engineer - Filters
Bethlehem, Pennsylvania, United States
OnsiteFull Time
Bachelor's in Mechanical Engineering (or related) required; manufacturing experience preferred; skills in product design, drawings, BOMs, hydraulic/stress analysis, test verification, and cross-functional technical support.
SAP, SolidWorks
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FPGA Engineer
Amsterdam or Chicago or London or New York City or Singapore
OnsiteFull Time
Professional FPGA/ASIC design and verification experience; SystemVerilog/Verilog/VHDL and C++; familiarity with EDA tools and scripting (TCL, Python, Bash); university degree in EE/CS/CE or related.
SystemVerilog, Verilog, VHDL, C++, TCL, Python, Bash, EDA
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FPGA Engineer - Control Systems
Princeton, New Jersey, United States
$150k-$235k/yr OnsiteFull Time
Experienced in FPGA/ASIC digital logic design and verification, RTL and low-latency firmware for multi-domain clock systems; familiarity with Xilinx/AMD RFSoC platforms preferred.
RTL, FPGAs, ASICs, Xilinx, AMD, RFSoC
1mo
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Two Sigma Securities, Hardware Engineer
New York City, New York, United States
$165k-$300k/yr HybridFull Time
1+ YOEMinimum 1 year RTL design and verification experience, proficiency in SystemVerilog and Python, FPGA/ASIC knowledge, timing analysis, network protocol familiarity; C++ is a plus.
SystemVerilog, Python, FPGA, ASIC, C++
5d
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高性能プロセッサの低電力企画・評価・検証(1名募集)
Kanagawa or New York City
¥7800k/yr HybridFull Time
Experience in logic circuit design, semiconductor circuit design, or processor performance and power evaluation and verification. Daily conversational language ability required; Japanese conversational proficiency preferred.
Perl, Python
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