1mo
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Design Verification Engineer
Vancouver, British Columbia, Canada
$106k-$158k/yr HybridFull Time
Develop and execute verification test plans and testbenches using System Verilog/UVM; familiarity with RTL/Verilog, ASIC flows, simulators, and scripting; master's or bachelor's in electrical/computer engineering.
UVM, System Verilog, Verilog HDL, C, C++, Java, Perl, Ruby, Shell, UNIX, LINUX, VCS, NCSIM, Questa, Verdi, PCI Express, AMBA AXI, x86, ARM
1d
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Digital Design Verification Engineer
Markham or Vancouver
HybridFull Time
Experience in digital design verification using SystemVerilog and UVM, experience with protocol verification (PCIe, SATA, Ethernet), exposure to VCS and debug tools (Debussy/DVE/Verdi); bachelor’s or master’s preferred.
System Verilog, UVM, VCS, Debussy, DVE, Verdi
2mo
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Design Verification Engineer (1-Year Contract)
Ottawa or Markham or Vancouver
$128k-$192k/yr OnsiteContract
ASIC design verification engineer with Verilog/SystemVerilog/UVM experience; strong Linux/Windows, programming skills; knowledge of Makefile, Perl, Python, Ruby; ASIC design debugging.
Verilog, SystemVerilog, UVM, Linux, Windows, Makefile, Perl, Python, Ruby
2d
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Digital Design Verification Engineer
Markham or Vancouver
$128k-$192k/yr HybridFull Time
Experience developing SystemVerilog/UVM verification environments, implementing tests/checkers/coverage for PCIe/SATA/Ethernet, familiarity with simulation and debug tools; Bachelor's or Master's preferred.
System Verilog, UVM, VCS, Debussy, DVE, Verdi, AI tools
1d
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Performance Verification Engineer
Markham or Vancouver or Ottawa
$128k-$192k/yr HybridFull Time
Experience in IP/ASIC verification, UVM/SystemVerilog, Verilog, C/C++, SystemC/TLM, scripting (Perl/Ruby/shell), Linux/Windows, and a Bachelors or Masters in computer or electrical engineering.
UVM, Linux, Windows, Verilog, SystemVerilog, C, C++, SystemC, TLM, Perl, Ruby, Makefile, shell, PCIe, CXL, RTL, High-Level Synthesis (HLS)
2w
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Senior RTL Design Engineer
Markham or Vancouver or Ottawa
$155k-$233k/yr HybridFull Time
Hands-on RTL design and verification experience using Verilog HDL, AI-assisted RTL methodologies, multi-clock-domain design, lint/CDC closure, and high-speed I/O protocols; BSc in Computer or Electrical Engineering.
Verilog HDL
2w
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Principal RTL Design Engineer
Burnaby, British Columbia, Canada
$86k-$186k/yr OnsiteFull Time
2+ YOE2+ years ASIC development experience; strong RTL design/verification skills in Verilog/SystemVerilog/VHDL; experience with lab debugging, C/C++, scripting (Python, Perl, TCL, Shell); degree in electrical/computer engineering or related field.
Verilog, SystemVerilog, VHDL, C, C++, Python, Perl, TCL, Shell, oscilloscope, logic analyzer
1mo
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IP Validation Design Engineer
Vancouver, British Columbia, Canada
$155k-$233k/yr HybridFull Time
Bachelor’s or master’s in EE/CS, experience in digital logic design/verification and ASIC/post-silicon debug, scripting with Ruby/Python, lab equipment use, strong communication and problem-solving skills.
Ruby, Python, PCIe, CXL, UALINK, Oscilloscope, Logic Analyzer
1mo
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IP Validation Design Engineer
Vancouver, British Columbia, Canada
$136k-$233k/yr HybridFull Time
Bachelor's degree in EE/CS (Master's preferred). Experience in digital logic design/verification, ASIC and board/platform debug, scripting (Ruby, Python), lab equipment use, strong communication and teamwork skills.
Ruby, Python, protocol analyzers, logic analyzers, oscilloscopes, PCIe, CXL, UALINK
2mo
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Principal Engineer, Verification Platform
Burnaby, British Columbia, Canada
$220k-$275k/yr HybridFull Time
10+ YOE10+ years software engineering; distributed systems; internal platform/API design; IAM/OAuth/KYC familiarity; leadership through influence.
IAM, OAuth, KYC, APIs, Distributed systems, Platform services, Developer experience, Code reviews
2mo
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SoC Development Engineer
Vancouver, British Columbia, Canada
$91k-$135k/yr HybridFull Time
Bachelor’s in EE/CE/CS with strong debugging, digital logic design, RTL/verification (UVM/FPV); proficient in C/C++, Python, Verilog/SystemVerilog; internship/1+ year experience preferred.
C, C++, Python, Java, Verilog, SystemVerilog, UVM, FPV, Jira, Confluence, NVMe, PCIe, DDR, ARM
2w
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SoC Development Engineer
Vancouver, British Columbia, Canada
$134k-$201k/yr HybridFull Time
8+ YOEBachelor's in EE/CE/CS, strong digital logic and debugging skills, experience with RTL design, UVM and formal property verification, familiarity with Verilog/VHDL/SystemVerilog and C/C++/Python/Java. Advanced experience preferred.
C, C++, Python, Java, Verilog, VHDL, SystemVerilog, UVM, FPV
6d
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AI and Automation Software Engineer
Markham or Vancouver or Ottawa
$187k-$281k/yr HybridFull Time
Design and deliver AI-enabled automation tools to improve silicon verification and validation; proficiency in Python, CI/CD, cloud, containers, and collaboration; bachelor’s in EE/CS required or master’s preferred.
LangChain, LaMDA, AWS, Azure, Google Cloud Platform, Docker, Kubernetes, TensorFlow, Python, C, C++, JavaScript, Jenkins, GitHub Actions, Git, pytest, HTML, CSS, React, Angular, Node.js, SQL, NoSQL, Doxygen, Sphinx, CI/CD
1mo
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Superconducting IC Designer II
Burnaby, British Columbia, Canada
$125k-$171k/yr OnsiteFull Time
0+ YOEPost-secondary degree in electronic engineering, physics, computer science or related; 0–4 years IC design experience (0–2 for grad degree, 2–4 for bachelor); strong EM theory, programming and problem-solving; experience with EDA tools and IC verification.
EDA, Ansys, Keysight ADS, Cadence EDA tools, Comsol, SUN Magnetics modelling tools, WRspice, Common Lisp, Python, Cadence SKILL