33 design verification engineer jobs at 15 companies in Isleton, CA
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IP Design Verification Engineer
Phoenix or Chandler or Hillsboro or Folsom or Santa Clara
$142k-$200k/yr OnsiteFull Time
3+ YOEDegree in EE/CE (or related) with relevant years of experience; 3+ years in SystemVerilog/Verilog and UVM/OVM; experience with Synopsys VCS, Cadence Xcelium/JasperGold, or Mentor Questa; analog behavioral modeling and PCIe/UCIe experience.
System Verilog, Verilog, UVM, OVM, Synopsys VCS, Cadence Xcelium, JasperGold, Mentor Questa, PCIe, UCIe
1w
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Staff Design and Verification Engineer, Pathfinding
Folsom or Boise or San Jose
$116k-$246k/yr OnsiteFull Time
4+ YOE4+ years verification experience in digital/analog/mixed-signal, expertise in Verilog, FastSpice, co-simulation, SPICE, UNIX and Cadence; strong circuit and semiconductor physics knowledge and problem-solving skills.
Verilog, FastSpice, UNIX, Cadence, SPICE
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Staff Design and Verification Engineer, Pathfinding
Folsom or Boise or San Jose
$116k-$246k/yr OnsiteFull Time
4+ YOE4+ years verification experience in digital/analog/mixed-signal; expertise in Verilog, SPICE/FastSpice, co-simulation, real-number modeling; proficiency with UNIX and Cadence; BS/MS/PhD in electrical or related field or equivalent experience.
Verilog, FastSpice, SPICE, UNIX, Cadence, Artificial Intelligence (AI)
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Intern - Design Verification Infrastructure Engineer - Platform
Santa Clara or Austin or Berkeley or Boston
OnsiteFull Time
Software engineering experience with a compiled and a scripting language, modern engineering practices, production deployments; familiarity with Chisel/CIRCT/MLIR and EDA flows preferred.
Chisel, CIRCT, MLIR, Scala, Python
3mo
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
6+ YOEBachelor's or Master's in Electrical/Computer Engineering; 6-10 years VLSI design/verification; Verilog/SystemVerilog/UVM; scripting (Python/Perl/TCL); C/C++; EDA/verification tools.
Verilog, SystemVerilog, UVM, Specman, Python, Perl, TCL, C, C++, EDA tools
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
6+ YOE Bachelor's or Master in Electrical or Computer Engineering; 6-10 years in VLSI design/verification; scripting and programming experience; strong VLSI knowledge.
Python, Perl, TCL, C, C++, Verilog, SystemVerilog, UVM, Specman
3mo
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
6+ YOE6-10 years in VLSI design/verification; BS/MS in Electrical or Computer Engineering; scripting (Python/Perl/TCL); programming (C/C++); Verilog/SystemVerilog; UVM; knowledge of EDA tools.
Verilog, SystemVerilog, UVM, Python, Perl, TCL, C, C++
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Principal Engineer - Design
Roseville, California, United States
$75k-$232k/yr OnsiteFull Time
10+ YOE10+ years experience in SoC design/verification, BS/MS in Electrical/Computer Engineering, experience with serial protocols (SAS/SATA/NVMe, PCIe), Linux and C/Python scripting, RTL (VHDL/Verilog/System Verilog).
Cadence Palladium, Protium, Linux, C, Python, Tcl, Bash, VHDL, Verilog, System Verilog, JTAG, I2C
2mo
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Principal Systems Design Engineer
Folsom, California, United States
$175k-$300k/yr OnsiteFull Time
10+ YOEBachelor's in electrical or computer engineering with 10+ years of experience; strong hardware/software systems design, verification, and leadership skills.
3w
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Senior Electrical Engineer — Verification & Test
Alameda, California, United States
OnsiteFull Time
5+ YOEBachelor's in electrical engineering,5+ years experience,hands-on lab debugging,verification protocol development,custom test hardware design,Altium and scripting experience,knowledge of FDA design controls/ISO 13485.
Altium Designer, Python, MATLAB, LabVIEW, TestStand, National Instruments, Keithley
2w
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Principal Engineer, SOC Design
Folsom, California, United States
$199k-$319k/yr OnsiteFull Time
15+ YOEExtensive SoC architecture and RTL development experience with modern DRAM technologies, verification/debugging skills, FPGA prototyping or silicon bring-up experience, and strong technical leadership.
SystemVerilog, Verilog, FPGA
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IP Logic Design Engineer
Rancho Cordova, California, United States
$105k-$165k/yr OnsiteFull Time
7+ YOEMS in ECE with 7+ years or BS with 9+ years; expertise in Verilog/SystemVerilog and ASIC flow (RTL, synthesis, STA, ECO); experience with lint, CDC/RDC analysis, verification tools, scripting, and pre/post-silicon debug; 3D NAND experience preferred.
SystemVerilog, Verilog, RTL, synthesis, Static Timing Analysis (STA), ECO, lint tools, CDC/RDC analysis, SystemVerilog Assertions (SVAs), Gate-level simulation (GLS), Design for Testability (DFT)
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Senior Hardware Test Engineer
Fremont or California or United States
$170k-$221k/yr HybridFull Time
5+ YOE5+ years in test engineering/design verification for electrical or mechatronic systems; experience with actuators, motor controllers, sensors, EtherCAT, lab instrumentation, Python scripting, and subsystem-level verification; BS in related field required.
EtherCAT, Python, oscilloscopes, logic analyzers, DAQs, power supplies, environmental test equipment, motor controllers, PCBAs, sensors
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Manager, Mechanical Design Engineering
Berkeley, California, United States
$192k-$223k/yr OnsiteFull Time
7+ YOE2+ MgmtBachelor’s in Mechanical Engineering,7+ years mechanical design experience,2+ direct reports,FEA and SolidWorks proficiency,DFMA and sheet metal expertise,GD&T (ASME Y14.5-2018),ability to lead verification and production transitions.
SolidWorks, FEA, GD&T (ASME Y14.5-2018)
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Sr. Systems Engineer, Medical Device
Union City, California, United States
$130k-$150k/yr OnsiteFull Time
5+ YOEBachelor's in engineering (5+ years) or advanced degree with relevant experience; strong systems engineering, analytical, and testing skills; experience with design history files, verification/validation, and Office/MATLAB/LabVIEW tools.
MATLAB, LabVIEW, EA, Microsoft Outlook, Microsoft Excel, Microsoft Word, Microsoft PowerPoint, Microsoft Visio, Microsoft Project
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Staff Development Quality Engineer
Pleasanton, California, United States
$114k-$228k/yr OnsiteFull Time
9+ YOEBachelor's degree, 9+ years related experience, strong knowledge of design controls, verification/validation, FMEA, statistical techniques, and US FDA regulations; master's preferred.
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Staff Development Quality Engineer
Pleasanton, California, United States
$114k-$228k/yr OnsiteFull Time
9+ YOEBachelor's degree and minimum 9 years relevant experience; expertise in design controls, risk evaluation (FMEA), verification/validation, FDA/regulatory compliance, and cross-functional collaboration.
2mo
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Director of Mechanical Engineering, Hardware Platform
Emeryville or Santa Clara
$275k-$320k/yr HybridFull Time
15+ YOE7+ Mgmt15+ years robotics/precision automation; 7+ years leading engineering teams; strong mechanical design, GD&T, DFMEA/PFMEA; prototype-to-production leadership; cross-functional collaboration.
CAD, GD&T, DFMEA, PFMEA, DVP&R, Verification and Validation, Calibration, Testing
1w
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Prototyping Product Manager
Fremont or San Diego or Santa Clara or Wilsonville
$90k-$162k/yr HybridFull Time
1+ YOE1+ years product or technical program experience; familiarity with semiconductor design, EDA, or verification; strong analytical and communication skills; bachelor’s in engineering or CS preferred; ability to travel; U.S. work authorization required.
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