30 design verification engineer jobs at 18 companies in Laurel, MD
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
2+ YOEUS citizenship and ability to obtain U.S. Secret clearance; BS in engineering or related field; experience with ASIC/FPGA design or verification and HDL (Verilog/VHDL/System Verilog); familiarity with verification methodologies and scripting.
Verilog, VHDL, System Verilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, JESD204C, PCIe, Ethernet
2w
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FPGA Verification Engineer, Bespoke Solutions
Jessup or Arlington or Herndon
$136k-$184k/yr OnsiteFull Time
4+ YOERequires US citizenship and active TS/SCI clearance; Bachelor's in electrical/communications engineering; 3+ years design and 4+ years verification experience with SystemVerilog/UVM; FPGA/ASIC verification experience.
SystemVerilog, UVM, Xilinx Vivado, AMD Vivado, Synopsys VCS, Cadence Xcelium, SystemVerilog Assertions (SVA)
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
2+ YOEUS citizenship with ability to obtain U.S. Secret clearance, Bachelor\u0000s degree in a relevant field, experience with ASIC/FPGA design or verification, and RTL experience with Verilog/VHDL/SystemVerilog.
Verilog, VHDL, SystemVerilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, ARM, JESD204C, PCIe, Ethernet
2w
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Senior ASIC Digital Design Engineer
Annapolis Junction or Boise or Salt Lake City or Bloomington or United States
$142k-$150k/yr RemoteFull Time
5+ YOEBachelor's in Electrical/Computer Engineering (or related) with 5+ years experience (Master's+3 acceptable), U.S. citizenship, ability to obtain DoD Secret clearance, 5–8+ years ASIC/FPGA RTL design experience, formal verification and verification-process experience, JIRA and Microsoft Office proficiency.
JIRA, Microsoft Office, STA
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Digital Design Engineer - Level 5 - Linthicum
Linthicum Heights, Maryland, United States
$186k-$279k/yr OnsiteFull Time
7+ YOEDegree in EE/CE/CS or related with 7–12+ years experience, FPGA/ASIC/HDL (Verilog, VHDL) design and verification experience, FPGA tool usage (Xilinx, Microsemi), ability to mentor engineers, strong communication; U.S. citizenship and ability to obtain Top Secret clearance required.
Xilinx, Microsemi, Verilog, VHDL
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Digital Design Engineer - Level 5 - Linthicum
Linthicum, Maryland, United States
$186k-$279k/yr OnsiteFull Time
7+ YOEDegree in EE/CE/CS (Bachelor’s+12yr or Master’s+10yr or PhD+7yr), FPGA/ASIC/HDL (Verilog, VHDL) experience, FPGA IDEs (Xilinx, Microsemi), test/verification and RTL debug, mentoring skills, U.S. citizenship and ability to obtain Top Secret clearance.
Xilinx, Microsemi, HDL, Verilog, VHDL, RTL
2w
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Artificial Intelligence / Machine Learning Lead Verification and Validation Engineer
State College or Reston
$140k-$266k/yr OnsiteFull Time
14+ YOEBachelor's in CS/Data Science/Engineering, extensive experience designing/managing data curation, annotation, and IV&V workflows for AI/ML; Python and SQL proficiency; experience with annotation tools and data versioning; U.S. citizenship and clearance eligibility.
Python, SQL, CVAT, Label Studio, DVC, LakeFS, Docker, Kubernetes, AWS, Azure
3mo
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RF Engineer
Chantilly, Virginia, United States
OnsiteFull Time
12+ YOETS/SCI with polygraph, BS in Engineering or technical field, 12+ years experience in radar RF design and testing; on-site at Chantilly, US.
Radar, RF Design, System Testing, Verification
1w
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System Engineer (Door)
Hagerstown or Baltimore
$98k-$163k/yr OnsiteFull Time
3+ YOEBachelor's or master's degree in engineering and 3–5 years in railway or complex industrial environments. Requires systems engineering, railway standards, RAMS, IBM DOORS, design verification, and validation experience.
IBM DOORS, AutoCAD, Creo, Catia, Microsoft Word, Microsoft Excel, Microsoft PowerPoint
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Systems Engineer
King of Prussia or Springfield
$86k-$138k/yr OnsiteFull Time
0+ YOEActive TS/SCI clearance with polygraph required; BS in engineering/science with 2-4 years or MS with 0-2 years; knowledge of systems engineering, test design, data verification, and strong written/oral communication.
2w
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Staff/Senior Mechanical Engineer
Manassas, Virginia, United States
$93k-$126k/yr OnsiteFull Time
5+ YOEBachelor's degree in engineering and minimum 5 years relevant experience; mechanical system design, integration, verification, CAD (NX) proficiency, engineering analyses, and strong communication skills.
NX
6d
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Nuclear Systems Engineer
Bethesda, Maryland, United States
$110k-$240k/yr HybridFull Time
Bachelor's or advanced engineering degree or equivalent experience; direct reactor or complex thermal-energy system design experience; systems engineering expertise in requirements, interfaces, verification, configuration, and margins.
10 CFR Part 810, NRC, ABS, LR
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Staff Electrical Engineer
El Segundo or Los Angeles or Washington or San Francisco or San Diego or Seattle or London
$150k-$210k/yr OnsiteFull Time
8+ YOEBachelor's in Electrical Engineering with 8+ years experience in power and analog board design for high-reliability aerospace/defense systems; EMI/EMC, verification, production support, and ability to obtain U.S. security clearance.
1mo
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Centegix - Senior Test Engineer
Annapolis, Maryland, United States
OnsiteFull Time
6+ YOE6+ years test engineering in embedded systems; firmware verification; PCB design in Altium; Python test automation; Git; experience with lab diagnostic equipment, HIL, CI workflows, and soldering/assembly.
Python, AWS IoT, AWS CloudWatch, AWS Lambda, Altium, Git, Hardware-in-the-Loop (HIL), Continuous Integration (CI), CI/CD, oscilloscopes, logic analyzers, spectrum analyzers, function generators, 3D printers, CNC
3mo
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FPGA Engineer (VA, Reston )
Reston, Virginia, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and FPGA-based systems for hardware security; RTL/C/C++, Python, VHDL/Verilog; simulation, verification, system integration; verification tools and toolchains.
RTL, C/C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Xilinx, Versal, Agilex, AXI, ACE, Avalon, IP core, cocotb, pyuvm
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Application Engineer
San Jose or Austin or Cary or Columbia or Burlington
$74k-$138k/yr OnsiteFull Time
0+ YOEBachelor's degree in STEM required; entry-level new grad role with experience using EDA tools; familiarity with UNIX, C/C++, Perl, TCL, Python; fundamentals in design, verification, HDLs, synthesis, and timing.
Electronic design automation (EDA) tools, HDLs, UNIX, C/C++, Perl, TCL, Python
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Application Engineer
San Jose or Cary or Austin or Burlington or Columbia
$74k-$138k/yr OnsiteFull Time
Bachelor's degree in STEM required; entry-level cohort program for new graduates. Familiarity with EDA tools, fundamentals of design/verification, UNIX, C/C++, Perl, TCL, Python; strong communication and problem-solving skills.
Electronic Design Automation (EDA), UNIX, C/C++, Perl, TCL, Python, Hardware Description Languages (HDLs)
1w
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System Engineer - Fort Meade, MD - TS/SCI FS Poly
Fort Meade, Maryland, United States
$150k/yr OnsiteFull Time
5+ YOEBachelor's plus 5 years systems engineering experience, active TS/SCI with Full Scope Polygraph, experience with system design/integration/verification, strong analytical and communication skills.
MBSE, SysML
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Senior FPGA Engineer, Cyber
Washington, District of Columbia, United States
$166k-$220k/yr OnsiteFull Time
Deep FPGA/SoC design experience on Xilinx or comparable platforms; proficiency in VHDL/Verilog/SystemVerilog; high-speed interfaces, precision timing, verification, lab debugging, and cross-functional collaboration.
Xilinx, VHDL, Verilog, SystemVerilog, Lattice OS, cocotb, GitLab CI/CD, Linux, oscilloscope, logic analyzer, spectrum analyzer
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Senior FPGA Engineer
Fairfax, Virginia, United States
$76k-$141k/yr OnsiteFull Time
4+ YOEBachelor's in EE/CE (or MS) and 6+ years (4+ with MS) experience in FPGA RTL design, timing closure, simulation/verification, Vivado/VHDL/SystemVerilog experience, lab bring‑up, and high‑speed interface integration.
Xilinx, Zynq Ultrascale+ MPSoC, Zynq Ultrascale+ RFSoC, Versal ACAP, Versal AI Engines, Vivado Design Suite, Vivado IP Integrator, Vivado HW Debugger, Chipscope, SmartDebug, Libero, Git, Modelsim, Questasim, Aldec, UVVM, UVM, OVM, VHDL, SystemVerilog, MATLAB, Simulink, Linux, C, C++
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