43 design verification engineer jobs at 17 companies in Mesa, AZ
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Senior Design Verification Engineer
Tempe or Independence
$156k-$291k/yr RemoteFull Time
8+ YOE8+ years design verification experience with UVM, SystemVerilog, RTL verification for FPGA/ASIC, Bachelor's in EE/CE, US citizenship, ability to obtain Secret clearance, familiarity with Questa/Xcelium/VCS and AI verification tools.
Universal Verification Methodology (UVM), SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
2mo
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Senior CPU Design Verification Engineer
Austin or Phoenix
$142k-$200k/yr HybridFull Time
4+ YOE4+ years in design verification; SystemVerilog/UVM; pre-silicon CPU/SoC verification; strong debugging; Bachelor's or Master in Electrical or Computer Engineering.
SystemVerilog, UVM, EDA tools, Python, Linux
2mo
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Senior Design Verification Engineer
Tempe or Independence or Arizona or Ohio or San Jose or New York City
$142k-$224k/yr HybridFull Time
8+ YOE8+ years design verification experience with UVM and testbench development; Bachelor's in EE/CE or related; experience with Questa/Xcelium/VCS; AI/agentic DV experience preferred; US citizenship and ability to obtain Secret clearance; travel up to 10%.
UVM, SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
2mo
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Staff Design Verification Engineer (AI/ML)
Chandler, Arizona, United States
OnsiteFull Time
5+ YOEMS EE/CE with 7+ years or PhD with 5+ years (BSEE/BSCE considered); strong SystemVerilog/UVM and Python skills; experience delivering verification to tape-out; knowledge of formal verification and CDC; familiarity with Xcelium and JasperGold.
SystemVerilog, UVM, Python, Xcelium, JasperGold, Verilog-AMS, SDF
2mo
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Senior Design Verification Engineer (eInfochips Inc)
Minneapolis or Phoenix
OnsiteFull Time
Bachelor’s or Master’s in EE/CE or related; strong SystemVerilog and UVM skills; scripting with Python/Perl/Tcl; experience with Cadence Xcelium, Synopsys VCS or Siemens Questa; knowledge of constrained-random verification, SVA, functional coverage and AMBA protocols.
UVM, SystemVerilog, Python, Perl, Tcl, Cadence Xcelium, Synopsys VCS, Siemens Questa, Cadence Palladium, C, SVA, UPF, CPF, Real Number Models (RNM), AMBA (AXI/AHB/APB)
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Director, Digital Design & Verification
Chandler, Arizona, United States
OnsiteFull Time
Proven leader in digital IC design and verification for mixed-signal SoCs with expertise in RTL, verification methodologies (UVM, formal, AMS/DMS), architecture, and team building.
SystemVerilog, UVM, Formal, AMS/DMS, RTL, STA, DFT
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Design Engineer
Tempe, Arizona, United States
OnsiteFull Time
Coordinate and produce electrical distribution designs, use CAD and work management systems, perform field verifications, prepare material lists and cost estimates, ensure permitting and standards compliance.
CAD, Work Management System
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Sr Digital Design Engineer
Chandler, Arizona, United States
OnsiteFull Time
10+ YOEM.S. in electrical, computer, or related engineering; 10+ years in digital IC design; Verilog/SystemVerilog, EDA tools, synthesis, timing analysis, verification, UVM, and technical leadership experience.
Verilog, SystemVerilog, UVM, Cadence, Synopsys, Siemens EDA
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Electrical Design Engineer, Avionics Ground and Test Equipment III
Seattle or Phoenix or Huntsville or Denver or Los Angeles or Florida or Washington
$131k-$183k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
5+ YOEB.S. in computer or electrical engineering (required); 5+ years in electrical design, systems engineering, electronics integration, validation/verification, networking, scripting, and test equipment design; experience with data communication protocols and signal conditioning/A-D for HIL test equipment.
2mo
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Technical Staff Engineer - AMS Verification
Chandler, Arizona, United States
OnsiteFull Time
14+ YOEBachelor's/Master's in electrical engineering plus 14+ years experience, proven AMS verification for advanced SoCs (12nm+), strong PI/SI and silicon-debug skills, and hands-on use of Cadence Virtuoso/Spectre/AMS Designer, Questa ADMS/Symphony, HSPICE.
Cadence Virtuoso, Spectre, AMS Designer, Questa ADMS, Symphony, HSPICE, SPICE
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Package Layout Design Engineer , Annapurna Labs - AI Silicon Packaging
Tempe or Austin or Cupertino
$136k-$213k/yr OnsiteFull Time
5+ YOEBachelor's degree in electrical engineering or related field and 5+ years of IC package layout and physical design experience. Requires package layout tools, advanced packaging, DFM, and physical verification expertise.
Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, Python, Perl, ARM, TCL, Skill, Ravel, DRC
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Systems and Test Integration Engineer - FPGA Integration & Verification
Scottsdale, Arizona, United States
$91k-$101k/yr OnsiteFull Time
2+ YOEBachelor's in systems/engineering/math plus 2+ years (or Master's plus 6 months), TS/SCI clearance obtainable, FPGA design and hardware bring-up experience, RTL (SystemVerilog/VHDL), scripting (Python,Tcl), Linux and Git proficiency.
SystemVerilog, VHDL, Xilinx/AMD Vivado, Lattice Diamond, Radiant, Python, Tcl, Git, GitLab CI, RHEL, Ubuntu, Linux shell scripts, JTAG, oscilloscope, protocol analyzer
1mo
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Senior Electrical Engineer
Phoenix, Arizona, United States
$100k-$150k/yr OnsiteFull Time
6+ YOE6+ years electrical engineering experience in industrial/manufacturing/semiconductor design, PE required or pursuing, Bachelor's in Electrical Engineering, AutoCAD proficiency, knowledge of NEC/IBC/IFC/NFPA, field verification experience.
EasyPower, ETAP, SKM PowerTools, AutoCAD
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Principal Hardware Engineer
Phoenix, Arizona, United States
OnsiteFull Time
13+ YOEBachelor's with 15 years or master's with 13 years in hardware engineering; avionics lifecycle, safety-critical design, circuit and PCB development, verification, certification, and technical leadership experience required.
Electronic Design Automation, Mentor Graphics Xpedition, Mathcad, LTspice, Microsoft Excel, PCB, FPGA, ADC, DAC, DO-254, RTCA DO-160, simulation, laboratory test equipment
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Senior Electrical Engineer
Phoenix, Arizona, United States
$100k-$150k/yr OnsiteFull Time
6+ YOE6+ years electrical engineering experience in industrial/manufacturing/semiconductor facility design; ABET Bachelors in Electrical Engineering; PE license (or pursuing); AutoCAD proficiency; knowledge of NEC, IBC, IFC, NFPA; field verification and client presentation skills.
AutoCAD, EasyPower, ETAP, SKM PowerTools, BIM
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Senior Electrical Engineer (AZ, Scottsdale)
Scottsdale, Arizona, United States
OnsiteFull Time
Design, analyze, test, and troubleshoot analog, digital, mixed-signal, and embedded electronic systems; support system integration, verification/validation, manufacturing transfer, and sustaining engineering for medical devices.
2w
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Sr. Staff Systems Engineer
Tempe, Arizona, United States
OnsiteFull Time
4+ YOELead system architecture, define system requirements, drive integration/verification, ensure design control compliance; require engineering degree plus multi-year R&D experience and test method development expertise.
Modern Requirements, PTC, Polarion, JAMA, DOORS
1mo
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Principal Engineer Electrical
Gilbert, Arizona, United States
$98k-$148k/yr OnsiteFull Time
5+ YOEBachelor's in STEM +5 years (or Master's +3 / PhD +1) experience in RTL/HDL FPGA/ASIC design for aerospace/space, proficiency in FPGA design flow, verification, synthesis, timing and power analysis; strong communication and problem solving.
HDL, RTL, Xilinx ISE/Vivado, Mentor Graphics ModelSim/QuestaSim, Synplify, System Verilog, Universal Verification Methodology (UVM), Signal Generators, Logic Analyzers, Digital Oscilloscopes, Embedded FPGA Debugging tools
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Systems Engineer - Level 4
Chandler, Arizona, United States
$123k-$184k/yr OnsiteFull Time
6+ YOEU.S. citizen with active DoD security clearance (Secret). Bachelor\u0000s +8 years or Master\u0000s +6 years experience. Experience in requirements management, system integration, verification/validation, and system design analyses.
RS-485, Ethernet, ARINC-429, CAN, GPS, INS, FPGAs, D38999
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DFT Engineer (CE-64000920)
Austin or Chandler or Greensboro
HybridFull Time
2+ YOEMSEE with 2+ years or BS with relevant experience; hands-on ASIC DFT design and verification; experience with FastScan, TestKompress, TetraMAX, Test Compiler; MBIST, scan/ATPG, Verilog/SystemVerilog/VHDL; scripting (Perl, Python, TCL); strong communication.
FastScan, TestKompress, TetraMAX, Test Compiler, Verilog, SystemVerilog, VHDL, Perl, Python, TCL
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