1mo
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DFT Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years DFT experience including specification, architecture, insertion and analysis; silicon bring-up/debug/validation of DFT features; fault modeling; ATPG/MBIST/JTAG/ATE experience; strong problem-solving and communication skills.
Design/Fusion Compiler, DFT Max, SpyGlass, Modus, Tessent, TestKompress, ATPG, MBIST, JTAG, ATE
3mo
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SoC DFT Engineer
Austin or Cupertino
OnsiteFull Time
3+ YOEBS with at least 3 years of experience in silicon DFT; strong Verilog/VHDL and DFT tool knowledge.
Verilog, VHDL, Simulators, Waveform Debugging, Scripting, DFT tools
1mo
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DFT Engineer
Austin, Texas, United States
$129k-$207k/yr OnsiteFull Time
8+ YOEBSEE with 12+ years or MSEE with 8+ years, strong DFT knowledge including MBIST, scan insertion, ATPG, silicon bring-up and yield improvement, Mentor Tessent/Synopsys experience, and Perl scripting.
Mentor Tessent, Synopsys, Perl
1mo
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Principal DFT Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years DFT implementation and verification experience including scan architectures, JTAG, memory MBIST, ATPG; Verilog/VHDL RTL knowledge; ability to handle RTL DFT changes, analyze ATPG/DRC reports, and support test pattern bring-up.
RTL, MBIST, ATPG, JTAG, TAP, ATE, Verilog, VHDL, SDF
2mo
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Principal Test Engineer/DFT Architect
Austin, Texas, United States
OnsiteFull Time
12+ YOEDefine product-level test/DFT strategy; lead cross-functional DFT efforts; mentor engineers; 12+ years in semiconductor test/DFT; strong ATE experience.
ATE, DFT, signal measurement, scripting, Python, MATLAB, SQL
2mo
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Principal DFT Engineer (Silicon Engineering)
Austin or Irvine or Sunnyvale
OnsiteFull Time
10+ YOEBachelor’s in electrical/computer engineering or computer science; 10+ years in ASICs and DFT, including scan insertion and validation.
Siemens Tessent, ATPG, Verilog, SystemVerilog, UPF, Formal verification, DRC, Python, Perl, Tcl, C++
3w
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Sr. Staff Engineer - DFT
Austin, Texas, United States
OnsiteFull Time
10+ YOEBS/MS in ECE/EE with 10+ years DFT experience; skilled in scan, scan compression, boundary scan, MBIST, low-power DFT, ATPG and RTL; experience with Tessent MBIST flow, Cadence Genus/Modus, and scripting (Tcl, Perl, Python).
Cadence Genus, Modus, Tessent, Tcl, Perl, Python
5d
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DFT Implementation Engineer
Austin, Texas, United States
$142k-$200k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE,5+ years DFT/SoC design experience, RTL design (Verilog/VHDL/SystemVerilog), ATPG/scan/MBIST experience, Tessent and industry DFT tool knowledge, scripting (TCL/Perl/Python).
Tessent Shell, SSN, Tessent Fast IO, ISTK, Siemens EDA (Mentor) Tessent, Synopsys DFT Compiler, Cadence Modus, ATPG, MBIST, Verilog, VHDL, SystemVerilog, TCL, Perl, Python, UPF
3w
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ASIC DFT Engineer
San Jose or Austin
$165k-$241k/yr HybridFull Time
7+ YOEBachelor's or Master's in Electrical/Computer Engineering with 7+ years experience in DFT, ATPG, Jtag/scan/BIST, EDA tools (TestMax/Tetramax/Tessent/PrimeTime), gate-level simulation, and post-silicon validation.
Jtag, BIST, ATPG, TestMax, Tetramax, Tessent, PrimeTime, VCS, P1687, System Verilog, Verilog
1mo
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DFT Engineer (CE-64000920)
Austin or Chandler or Greensboro
HybridFull Time
2+ YOEMSEE with 2+ years or BS with relevant experience; hands-on ASIC DFT design and verification; experience with FastScan, TestKompress, TetraMAX, Test Compiler; MBIST, scan/ATPG, Verilog/SystemVerilog/VHDL; scripting (Perl, Python, TCL); strong communication.
FastScan, TestKompress, TetraMAX, Test Compiler, Verilog, SystemVerilog, VHDL, Perl, Python, TCL
1mo
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DFT Design Engineer
Austin, Texas, United States
OnsiteFull Time
2+ YOEUS citizenship required. 2+ years SoC/ASIC digital design experience focused on DFT, including scan chain insertion, compression scan, MBIST/LBIST, ATPG, JTAG/IEEE standards, Verilog testbench debugging, and familiarity with Cadence tools/flows.
Cadence tools and flows, Verilog, ATPG, MBIST, LBIST, JTAG 1149.1/6, IEEE1500, IEEE1687
2mo
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Sr. DFT Design Engineer, AWS Machine Learning Acceleration
Austin, Texas, United States
$159k-$215k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC design; DFT, ATPG, JTAG, MBIST; scripting; collaboration with PD/architecture; RTL through silicon experience.
ATPG, JTAG, MBIST, RTL, Python, Perl, Tcl, DFT/SCAN/ATPG tools
1mo
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Principal SLT Test Engineer
Austin, Texas, United States
OnsiteFull Time
Proven functional/ATE test engineering background, experience with SLT, DFT and production test, scripting skills (Python, TCL, Perl, Shell), degree in electronics or related field, ability to lead and mentor engineers.
SLT, ATE, DFT, JTAG, BIST, MBIST, Python, TCL, Perl, Shell
1mo
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Senior Test Engineer
Hillsboro or Austin or Redmond or Mountain View
$120k-$235k/yr HybridFull Time
1+ YOEAdvanced degree or equivalent experience in EE/CE/CS with technical engineering experience; expertise in scan/DFT/ATPG, ATE test development (scan), silicon bring-up, debug, and yield analysis; ability to pass Microsoft background and export-control screenings.
Advantest 93K, Linux, ATPG, DFT, JTAG
1mo
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System Software Engineer
Austin, Texas, United States
HybridFull Time
Design and develop Scandump/JTAG/scan tools, work across DFT/firmware/hardware/software teams, coordinate/debug issues, drive continuous improvement; preferred experience with C#, Python, SQL, C++, Verilog, x86 and software+hardware platforms; Bachelor's or Master's in Computer or Electrical Engineering preferred.
C#, Python, SQL, C++, Verilog, X86, JTAG, Scandump, DFT
3mo
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Senior Electrical Engineer – PCBA Schematic & Layout
Austin, Texas, United States
OnsiteFull Time
3+ YOE3+ years PCB schematic/layout experience; Bachelor's in Electrical Engineering; Proficiency in Altium Designer; multi-layer high-speed design; DFM/DFT; strong problem solving and documentation.
Altium Designer, SPICE, DFM/DFT tooling
3mo
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Senior RTL Engineer/Lead
Austin, Texas, United States
$152k-$255k/yr OnsiteFull Time
8+ YOE8+ years RTL design experience for complex IP/CPU subsystems, strong SystemVerilog/Verilog and synthesis skills, front-end quality flow knowledge, scripting (Perl/Python/Tcl), and collaboration with DV/DFT/PD teams.
SystemVerilog, Verilog, Perl, Python, Tcl, Lint, CDC, LEC
5d
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DV Engineer - AI
Austin, Texas, United States
$60k-$135k/yr OnsiteFull Time
5+ YOE5+ years VLSI/HVL verification experience with SV/UVM, AMBA knowledge, testplan and coverage experience, debug skills, and AI/LLM familiarity.
SV, UVM, AMBA, System Verilog, UPF, CPF, RTL, DFT, HVL, LLMs
1mo
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Senior ASIC Floorplan Design Engineer
Santa Clara or Austin
$196k-$311k/yr OnsiteFull Time
10+ YOEMSEE/MSCE or equivalent experience, 10+ years in chip development, expertise in SOC/CPU/graphics floorplanning and physical design, experience with power/clock/DFT/place-and-route/timing, and programming in Python/Perl/C++.
Python, Perl, C++
1mo
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Senior ASIC Floorplan Design Engineer
Santa Clara or Austin
$196k-$311k/yr OnsiteFull Time
10+ YOEMSEE/MSCE or equivalent experience, 10+ years in chip development; expertise in SOC/CPU/graphics/memory/I/O subsystems, physical design methodologies, chip floorplan, power/clock/reset distribution, DFT, place-and-route, timing closure, packaging; Python/Perl/C++ and AI workflows experience.
Agentic AI workflows, Python, Perl, C++