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Sr. Design for Test (DFT) Engineer
Toronto or Mountain View or Boston
HybridFull Time
13+ YOEBachelor's in Electrical Engineering, 13+ years DFT experience on ASICs, 2+ tapeouts, experience with DFT CAD/ATPG, Python/TCL scripting, post-silicon bring-up and ATE interfacing.
Python, TCL, SystemVerilog, ATPG, ATE
4d
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Sr. Design for Test (DFT) Engineer
Mountain View or Boston or Toronto
$164k-$185k/yr HybridFull Time
5+ YOEBachelor's in EE/CE,5+ years DFT experience for advanced ASICs,pre- and post-silicon validation,Python/TCL scripting,Verilog,knowledge of scan/ATPG/MBIST/JTAG and commercial EDA DFT tools.
Python, TCL, Verilog, ATPG, MBIST, JTAG, ATE
4d
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Sr. Design for Test (DFT) Engineer
Boston or Mountain View or Toronto
$154k-$218k/yr HybridFull Time
5+ YOEBachelor's in EE/CE,5+ years DFT experience for advanced ASICs,pre-/post-silicon validation,Python/TCL scripting,Verilog,ATPG/MBIST/JTAG expertise,commercial EDA DFT tool experience.
Python, TCL, Verilog, ATPG, MBIST, JTAG, Boundary Scan, ATE
1w
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Lead Principal Engineer Test
Leominster, Massachusetts, United States
$162k-$223k/yr OnsiteFull Time
10+ YOEBS in Engineering or Materials Science, 10+ years semiconductor test engineering, hands-on ATE (Teradyne, Advantest), DFT knowledge, test hardware design, leadership and problem-solving skills.
ATE, Teradyne, Advantest
2mo
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ASIC Physical Design Engineer
Maynard or Austin
$136k-$195k/yr HybridFull Time
5+ YOEBachelors in Engineering with 5+ years or Masters in Engineering with 3+ years in ASIC physical design; experience with floorplanning, place-and-route, STA, timing closure, DFT collaboration, scripting, and design flow optimization.
Cadence Innovus, Synopsys ICC2, Synopsys DC/FC, Synopsys Formality, Cadence LEC, Tempus, Python, TCL, Perl
2w
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Senior Manufacturing Engineer
Cambridge, Massachusetts, United States
$202k-$270k/yr OnsiteFull Time
8+ YOE8+ years manufacturing/process engineering experience delivering electromechanical products; DFx, NPI, quality systems, GD&T, tolerance and BOM experience required.
DFx, DFM, DFA, DFT, FAI, PPAP, SPC, FMEA, CAPA, GD&T, BOM
1mo
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Interconnect Micro-architect/RTL Design Engineer
Austin or Boxborough
$156k-$268k/yr HybridFull Time
Experienced RTL design engineer with strong Verilog/System Verilog skills, knowledge of C/C++ and scripting (Perl or Python), digital/high-speed design understanding, and experience with multi-processor coherency, DFT-friendly RTL and post-silicon debug.
Verilog, System Verilog, C, C++, Perl, Python, x86, ARM
1mo
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Platform - Digital Systems Engineer (North Reading, MA, US)
North Reading, Massachusetts, United States
OnsiteFull Time
10+ YOE10+ years engineering experience with system-level hardware/software expertise; strong digital DFT, ATE and semiconductor test knowledge; proven technical leadership, architecture decision-making, and ability to travel 10–20%.
UltraFLEXplus, ATE
1d
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Foundry Technology Engineer
Holmdel or Maynard
$155k-$225k/yr HybridFull Time
4+ YOEMS or PhD in EE/Optics/Photonics, 4+ years foundry/process qualification experience, wafer-level testing and lab automation experience, DFM/DFR/DFT knowledge, foundry/vendor management, strong communication and technical leadership.
Cadence Virtuoso, Synopsys, ANSYS Lumerical
1mo
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Principal Engineer Yield & Product
Andover, Massachusetts, United States
$146k-$201k/yr HybridFull Time
15+ YOEBSEE and 15+ years in semiconductor industry; expertise in mixed-signal electronics, silicon manufacturing, test platforms and analysis tools; experience with yield, DfT, NPI, failure analysis; up to 10% travel.
Synopsis Silicon. da, Galaxy Examinator, JMPdata, V93K, Teradyne (Eagle) ETS, J750
1mo
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Senior LPU ASIC Engineer
Santa Clara or California or North Carolina or Oregon or Arizona or Massachusetts or United States
$136k-$265k/yr HybridFull Time
5+ YOEB.S. in ECE or equivalent with 5+ years delivering full‑flow physical design for large SoCs; expertise in RTL-to-GDSII flow, low-power (UPF), timing/CTS, PPA optimization, sign-off integrity, DFT, and scripting (TCL/Python/Perl).
TCL, Python, Perl
1mo
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Senior Electrical Engineer
Cypress or Andover
OnsiteFull Time
4+ YOEBachelor's in EE/CE, typically 4+ years board-level hardware design experience, proficiency with FPGAs and high-speed interfaces (PCIe, DDR, Ethernet), strong signal-integrity knowledge, design documentation, and mentorship experience. U.S. person required for export-controlled work.
100G+ Ethernet, PCIe Gen 3/4, DDR4/5 SDRAM, fiber optics, HD-SDI, LVDS, Intel, Xilinx, Altera, NVIDIA, Broadcom, TI, SATA, I2C, ARINC-429, Ethernet, Cadence Allegro, JAMA, DOORS, JIRA, Confluence, 100G/200G Ethernet, PCIe Gen4/Gen5, DDR4/DDR5, Mellanox, Marvell, Agilex, Versal, DFR, DFM, DFC, DFT
4d
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Principal Technical Engineer 3rd Party IP Engineer
Morrisville or Austin or New York or Burlington or Westborough or Boise
$152k-$225k/yr OnsiteFull Time
3+ YOEBachelor’s in CS/EE with 5-10 years or Master/PhD with 3-5 years; deep DDR/LPDDR/GDDR/HBM/eMMC interface knowledge, ASIC design flow experience, 3rd-party IP management, project and customer communication skills.
DDR, LPDDR, GDDR, HBM, eMMC, logic synthesis, physical design, timing, DRC/LVS, Formal verification, Design-For-Test, DFT
2mo
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Principal/Lead Hardware Engineer (Teradyne, North Reading, MA) (North Reading, MA, US)
North Reading, Massachusetts, United States
$141k-$226k/yr OnsiteFull Time
10+ YOE10+ years hardware design; digital/analog, high-speed interfaces, embedded systems, PCB design, DFM/DFT; leadership and mentoring.
Cadence Allegro, Altium Designer, OrCAD
2w
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Principal Engineer Test
Andover, Massachusetts, United States
$146k-$201k/yr OnsiteFull Time
10+ YOEBachelor's degree in EE/Elec/Physics/Comp Eng, 10+ years developing ATE test solutions for mixed-signal ICs, ATE and test-programming experience, PCB and DfT knowledge, strong problem-solving and communication.
Cadence Allegro, C, C++, Java, Visual Basic, LabVIEW, Advantest V93K, Teradyne J750, Ultra Flex, Teradyne Eagle, ATPG, signal generator, oscilloscope, spectrum analyzer
1w
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Research Associate - Chemical and Biological Engineering
Medford, Massachusetts, United States
OnsiteFull Time
3+ YOEPhD and ≥3 years postdoctoral experience, strong DFT background (light-matter and solid-liquid interfaces), publication record, excellent communication; Python and AI/ML experience preferred.
Python
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