HiringCafe
Join our community

200 dft engineer jobs at 61 companies in San Jose, CA

3w
Save
Mark Applied
Hide
DFT Engineer
Mountain View, California, United States
$45k-$121k/yr OnsiteFull Time
Wipro
WiproNew York Stock Exchange: WIT: Global provider of IT consulting and business process services.
3+ YOERequires 3–5 years of DFT experience, VLSI physical place and route, scan, MBIST, ATPG, DFT verification, Verilog/SystemVerilog, and industry-standard DFT tools.
Tessent, Synopsys DFT Compiler, TetraMAX, TestMAX ATPG, Modus, Verilog, SystemVerilog, IJTAG, JTAG
Job PostingView all
3d
Save
Mark Applied
Hide
DFT Engineer, Google Cloud
Sunnyvale, California, United States
$138k-$197k/yr OnsiteFull Time
Google
GoogleNASDAQ: GOOGL: Provides online search, advertising, cloud computing, and consumer electronics.
3+ YOEBachelor's degree or equivalent practical experience, 3 years in DFT architecture, implementation, ATPG, and SoC verification, plus experience with test methodologies, platforms, and DFT tools.
Automatic Test Pattern Generation (ATPG), ATE, MBIST, JTAG, System Level Test (SLT), Electronic Design Automation (EDA), Synopsys, Design Compiler, DFT Max, Siemens EDA, Tessent, TestKompress, Scan, iJTAG, TAP
Job PostingView all
1mo
Save
Mark Applied
Hide
Senior DFT Engineer
Santa Clara, California, United States
$168k-$311k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
6+ YOEMS/PhD or equivalent in electrical engineering, 6+ years DFT experience, strong ATPG and DFT tool knowledge, ATE experience preferred, excellent communication, and mentoring ability.
ATPG, Automatic Test Equipment (ATE), EDA
Job PostingView all
1mo
Save
Mark Applied
Hide
Senior DFT Engineer
Santa Clara, California, United States
$168k-$311k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
6+ YOEMS/PhD or equivalent experience in Electrical Engineering, 6+ years DFT experience, deep knowledge of DFT/ATPG/EDA/ATE tools, strong communication and mentoring skills.
ATPG, EDA, ATE, CAD
Job PostingView all
3mo
Save
Mark Applied
Hide
Senior DFT Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
E-Space
E-Space: Builds sustainable LEO satellite networks for global IoT connectivity
8+ YOESenior DFT Engineer with 8+ years in design-for-test for complex digital ASICs/SoCs; expertise with DFT tools; RTL/ASIC test optimization.
Verilog, SystemVerilog, UVM, VHDL, Tcl, Python, Perl, Synopsys DFT Compiler, Tessent, DFTMAX, MBIST, JTAG, ATPG
Job PostingView all
2d
Save
Mark Applied
Hide
DFT Lead Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
10+ YOEBachelor's degree plus 12+ years or master's degree plus 10+ years in electrical, electronic, or computer engineering; strong DFT, ATPG, scan, BIST, Verilog, and semiconductor test experience.
TCL, Perl, Ruby, Python, C++, Verilog, DFT Compiler, Mentor TestKompress, TetraMax, Fastscan, ATE, IEEE 1149.1, IEEE 1149.6, IEEE 1687, IJTAG, ICL, PDL, Tessent SSN, SRAM, CAM, eDRAM, ROM, SerDes, DDR, PCIe, ENET, CXL
Job PostingView all
2mo
Save
Mark Applied
Hide
CPU DFT Engineer
Santa Clara, California, United States
$142k-$213k/yr OnsiteFull Time
Qualcomm
QualcommNASDAQ: QCOM: Designs and manufactures semiconductors and wireless telecommunications products.
5+ YOEDegree in EE/CE/CS (advanced degrees acceptable); senior-level ASIC/DFT experience (multi-year); Verilog/VHDL, Mentor Tessent, ASIC test/DFT/debug, SOC verification, TCL/Perl/Python/Shell scripting.
Verilog, VHDL, Mentor Tessent, TCL, Perl, Python, Shell
Job PostingView all
3w
Save
Mark Applied
Hide
DFT Staff Engineer
Santa Clara, California, United States
HybridFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Experience with DFT/ATPG and scan compression, Verilog logic design, post-silicon debug, Linux and scripting (Perl,Tcl); Bachelor's in EE/CE required, Master’s preferred.
ATPG, Tessent Scan/ATPG, Verilog, Linux, Perl, Tcl
Job PostingView all
1mo
Save
Mark Applied
Hide
ASIC DFT Engineer
San Jose or Austin
$165k-$241k/yr HybridFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
7+ YOEBachelor's or Master's in Electrical/Computer Engineering with 7+ years experience in DFT, ATPG, Jtag/scan/BIST, EDA tools (TestMax/Tetramax/Tessent/PrimeTime), gate-level simulation, and post-silicon validation.
Jtag, BIST, ATPG, TestMax, Tetramax, Tessent, PrimeTime, VCS, P1687, System Verilog, Verilog
Job PostingView all
2mo
Save
Mark Applied
Hide
Sr. ASIC DFT Engineer (Silicon)
Irvine or Austin or Sunnyvale
$125k-$150k/yr OnsiteFull Time
SpaceX
SpaceX: Designs and launches advanced rockets and satellite internet constellations.
5+ YOEBachelor's in engineering or physics; 5+ years in DFT/semiconductor testing; strong ASIC/DFT/ATE expertise.
Siemens Tessent, ATPG, Teradyne, Advantest, Perl, Python, Tcl, C++, IEEE 1500, IEEE 1687, IST
Job PostingView all
2mo
Save
Mark Applied
Hide
DFT Design Engineer
San Jose, California, United States
$143k-$207k/yr OnsiteFull Time
Altera
Altera: Manufacturer of field-programmable gate arrays and programmable logic devices.
5+ YOEDFT architecture and implementation, test logic insertion, ATPG, pre-silicon validation, EDA tool proficiency, scripting (Perl/TCL). Requires BS EE/CE +7 years or MS EE/CE +5 years experience.
EDA tools, ATPG tools, STA tools, Perl, TCL
Job PostingView all
1mo
Save
Mark Applied
Hide
DFT Design Engineering Director
San Jose, California, United States
$230k-$265k/yr OnsiteFull Time
Astera Labs
Astera LabsNASDAQ: ALAB: Designs connectivity solutions for cloud and AI infrastructure.
12+ YOE5+ MgmtMS/PhD in EE/CE or related, 12+ years DFT experience (5+ years leadership), deep expertise in 2.5D/3D packaging DFT, proven tape-out and production ramp experience, familiarity with DFT EDA tools and ATE platforms.
COSMOS, Synopsys DFT Compiler, TetraMAX, DFTMAX, Mentor Tessent, Advantest, Teradyne
Job PostingView all
3w
Save
Mark Applied
Hide
DFT Engineer (Architect / Manager / Sr. Manager)
Bangalore or Santa Clara
$200k-$500k/yr OnsiteFull Time
Velaura AI
Velaura AI: Developing ultra-low-power silicon and IP for AI accelerators.
15+ YOE15+ years in DFT architecture and execution for complex ASIC/SoC designs; expertise in scan, ATPG, MBIST/LBIST, MBIST, post-silicon debug, and cross-functional collaboration; leadership and mentoring experience.
Tcl, Python, Perl, ATE
Job PostingView all
4w
Save
Mark Applied
Hide
DFT CAD Engineer
Cupertino, California, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Seeking a passionate engineer to solve novel problems and contribute to the design and delivery of upcoming hardware products.
Job PostingView all
2w
Save
Mark Applied
Hide
Sr. Design for Test (DFT) Engineer
Toronto or Mountain View or Boston
HybridFull Time
Lightmatter
Lightmatter: Develops photonic processors and interconnects for AI data centers
13+ YOEBachelor's in Electrical Engineering, 13+ years DFT experience on ASICs, 2+ tapeouts, experience with DFT CAD/ATPG, Python/TCL scripting, post-silicon bring-up and ATE interfacing.
Python, TCL, SystemVerilog, ATPG, ATE
Job PostingView all
1w
Save
Mark Applied
Hide
DFT Design Engineer
Austin or San Jose
OnsiteFull Time
Cadence Design Systems
Cadence Design SystemsNASDAQ: CDNS: Develops computational software and hardware for electronic system design.
3+ YOE3-12 years SoC/ASIC digital design experience with focus on DFT, scan insertion, compression scan, MBIST, ATPG, EMR not required. US citizenship preferred.
Cadence, Verilog, ATPG, MBIST, JTAG 1149.1, JTAG 1149.6, IEEE1500, IEEE1687
Job PostingView all
1mo
Save
Mark Applied
Hide
Senior DFT Technical Manager
San Jose, California, United States
$179k-$286k/yr OnsiteFull Time
MediaTek
MediaTekTaiwan Stock Exchange: 2454: Designs and develops system-on-chip solutions for electronic devices.
10+ YOE10+ years DFT and silicon validation experience; deep knowledge of scan, ATPG, MBIST/LBIST, test coverage, silicon bring-up, diagnosis, and customer-facing technical leadership.
Synopsys TestMAX, TetraMAX, DFT Compiler, Siemens Tessent
Job PostingView all
1mo
Save
Mark Applied
Hide
Design for Test (DFT) Engineer
Mountain View, California, United States
$300k-$350k/yr OnsiteFull Time
DensityAI
DensityAI: Designing custom AI hardware accelerators for large language models.
7+ YOEBS/MS in EE/CE, 7+ years hands-on DFT experience across architecture, insertion, ATPG, BIST, boundary scan, verification and silicon test; deep Siemens Tessent expertise; scripting (Tcl, Python, Perl); familiarity with STIL/WGL and RTL (Verilog/SystemVerilog).
Siemens Tessent, STIL, WGL, Verilog, SystemVerilog, SDC, Tcl, Python, Perl
Job PostingView all
2w
Save
Mark Applied
Hide
Test Engineer
San Jose or Austin or Pittsburgh or Tucson
$150k-$190k/yr OnsiteFull Time
Efficient Computer
Efficient Computer: Developing ultra-low-power general-purpose processors for edge AI computing.
5+ YOE5+ years fabless or IDM semiconductor test experience, hands-on DFT, ATPG/MBIST/JTAG, ATE bringup on Advantest or Teradyne, OSAT coordination, yield analysis, and strong communication skills.
DFT, ATPG, MBIST, JTAG, STIL, PDL, SVF, Advantest, Teradyne, Python, Perl, VCD, RTL
Job PostingView all
3w
Save
Mark Applied
Hide
Principal Engineer, SOC Integration
San Jose, California, United States
$219k-$351k/yr OnsiteFull Time
Samsung Semiconductor
Samsung SemiconductorKorea Exchange: 005930: Designs and manufactures memory chips, processors, and sensors.
18+ YOEBS/MS in Computer/Electrical Engineering or CS with extensive ASIC/SoC experience (18+ years MS or 20+ years BS). Hands-on ASIC tape-out, commercial IPs (UCIe, CPU, DDR, Ethernet), SoC synthesis/timing/DFT, AMBA/ARM experience.
UCIe, ARM, DDR, Ethernet, AMBA, DFT, CDC
Job PostingView all

Explore Jobs

Expand Your Job Search