2w
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Senior DfT Engineer
Chandler, Arizona, United States
HybridFull Time
3+ YOEMaster's (MSEE) in relevant fields, 3+ years DfT/digital design experience, strong RTL coding and verification skills, Verilog/SystemVerilog proficiency, problem solving and communication skills.
Verilog, SystemVerilog
3mo
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Senior DFT Engineer (Einfochips)
San Jose or Arizona
RemoteFull Time
5+ YOE5-7 years DFT experience; scan insertion, ATPG, GLS, MBIST; IEEE 1149.1 JTAG; scripting (Perl, Shell, TCL); multi‑million gate SoCs in Networking/IPs; Mentor Tessent; strong communication; low power DFT.
Mentor Tessent, Cadence Modus, Synopsys Tetramax, Verdi, VCS
1mo
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DFT Engineer (CE-64000920)
Austin or Chandler or Greensboro
HybridFull Time
2+ YOEMSEE with 2+ years or BS with relevant experience; hands-on ASIC DFT design and verification; experience with FastScan, TestKompress, TetraMAX, Test Compiler; MBIST, scan/ATPG, Verilog/SystemVerilog/VHDL; scripting (Perl, Python, TCL); strong communication.
FastScan, TestKompress, TetraMAX, Test Compiler, Verilog, SystemVerilog, VHDL, Perl, Python, TCL
3mo
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Principal Digital Design Engineer
Chandler or Vancouver or Remote
$200k-$250k/yr HybridFull Time
10+ YOEBachelor's or master's in electrical/computer engineering; 10+ years in digital design with RTL; SoC/subsystem tapeout experience; strong RTL, microarchitecture, back-end flows, DFT/scan, LEC, STA, SDC skills; solid timing, power, and debug expertise.
Synopsys, Cadence, EDA tools, Synthesis, DFT, LEC, STA, SDC, UPF/CPF, RTL
2w
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Senior New Product Introduction Engineer, Electronics & Avionics - Lunar Permanence
Seattle or Phoenix or Brevard County or Huntsville or Denver or Los Angeles
$144k-$220k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBachelor's in electrical engineering or related,8+ years electronics manufacturing/NPI experience,PCBA/SMT experience,DFM/DFA/DFT expertise,contract manufacturer collaboration,and technical program management skills.
3w
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Principal Design Engineer
Chandler or Phoenix or Raleigh or Durham
OnsiteFull Time
10+ YOEBSEE/MSEE with 10+ years experience in precision analog/mixed-signal design; transistor-level design ownership, system-to-block requirements translation, DFT/simulation, EMR of product development; familiarity with Cadence AMS, JAMA, GIT; System Verilog desired.
Cadence Analog and Mixed Signal Tool Suite, JAMA, GIT, system Verilog
1mo
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Staff Digital Design Engineer (AI/ML)
Chandler, Arizona, United States
OnsiteFull Time
5+ YOEMS (EE/CE) with 7+ years or PhD with 5+ years (BSEE/BSCE considered); strong Verilog/SystemVerilog RTL and tape-out experience; Python/Tcl/shell scripting; Cadence Genus/Innovus/Tempus/Conformal; synthesis, STA, DFT knowledge.
Verilog, SystemVerilog, Python, Tcl, Shell, Genus, Innovus, Tempus, Conformal
1mo
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Coatings & Blasting Lead
Chandler, Arizona, United States
OnsiteFull Time
4+ YOE1+ MgmtMinimum 4 years abrasive blasting and protective coatings experience, 1 year leading crews, SSPC surface prep knowledge, proficiency with airless/HVLP/plural-component equipment, ability to perform DFT/WFT inspections, pass supplied-air respirator fit test and medical eval, lift 50 lbs and work at heights.
airless spray, HVLP, plural-component spray equipment, Graco, SSPC, AMPP, NACE, RCRA, OSHA 29 CFR 1910.134
1w
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Senior Connector Design Engineer
Mesa, Arizona, United States
OnsiteFull Time
7+ YOEBS in Mechanical/Aerospace/Electrical engineering,7+ years design experience,knowledge of MIL-STDs/IEC/ASTM,ISO 9001/AS9100,mentoring experience,and proficiency with RF simulation and PLM/MRP tools.
HFSS, ADS, CST, SolidWorks, PLM, MRP, FMEA, FEA, DFM, DFT
2mo
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Senior Digital Design Engineer
Chandler, Arizona, United States
OnsiteFull Time
3+ YOEMaster's degree in Electrical Engineering with emphasis on Digital Design; 3+ years in digital design/architecture; willing to relocate to Chandler/Phoenix area; strong problem solving and teamwork.
Verilog, SystemVerilog, HDL, Synthesis, STA, DFT
2mo
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Principal Analog Design Engineer
Chandler, Arizona, United States
HybridFull Time
12+ YOELead analog/mixed-signal PMIC design; 12+ years in power management; strong leadership and cross-cultural collaboration.
CMOS design, Analog circuit design, DFT, Simulation tools
1d
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Director, Digital Design & Verification
Chandler, Arizona, United States
OnsiteFull Time
Proven leader in digital IC design and verification for mixed-signal SoCs with expertise in RTL, verification methodologies (UVM, formal, AMS/DMS), architecture, and team building.
SystemVerilog, UVM, Formal, AMS/DMS, RTL, STA, DFT