1mo
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DFT Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years DFT experience including specification, architecture, insertion and analysis; silicon bring-up/debug/validation of DFT features; fault modeling; ATPG/MBIST/JTAG/ATE experience; strong problem-solving and communication skills.
Design/Fusion Compiler, DFT Max, SpyGlass, Modus, Tessent, TestKompress, ATPG, MBIST, JTAG, ATE
3mo
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SoC DFT Engineer
Austin or Cupertino
OnsiteFull Time
3+ YOEBS with at least 3 years of experience in silicon DFT; strong Verilog/VHDL and DFT tool knowledge.
Verilog, VHDL, Simulators, Waveform Debugging, Scripting, DFT tools
3w
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DFT Engineer
United States
$100k-$500k/yr RemoteFull Time
10+ YOEBachelor's/Master's/PhD in EE/CE/CS with 10+ years DFT experience; hands-on with Synopsys/Siemens tools, TCL and Python scripting; expertise in DFT planning, SoC debug, formal verification, and signoff.
Synopsys, Siemens, TCL, Python, ATPG, JTAG, memory BIST, RISC-V
3mo
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ASIC DFT Engineer
San Jose, California, United States
$141k-$226k/yr OnsiteFull Time
12+ YOEBachelor's with 12+ years or Master's with 10+ years in ASIC DFT; strong DFT background; ATPG/Scan/BIST experience; Verilog, memory BIST; IO/SerDes DFT; problem solving.
TetraMax, Fastscan, Mentor TestKompress, Serdes, DDR, PCIE, ENET, CXL
3w
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Senior DFT Engineer
Seattle, Washington, United States
$170k-$250k/yr OnsiteFull Time
7+ YOEB.S./M.S. in EE or related, 7+ years DFT experience for complex SoCs, RTL DFT insertion, ATPG and pattern generation, MBIST/LBIST, scan architectures, low-power DFT, mixed-signal test methods, and strong RTL/gate/silicon debugging.
ATPG, MBIST, LBIST, RTL, IEEE 1149.x (JTAG)
1mo
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Senior DFT Engineer
Santa Clara, California, United States
$168k-$311k/yr HybridFull Time
6+ YOEMS/PhD or equivalent in electrical engineering, 6+ years DFT experience, strong ATPG and DFT tool knowledge, ATE experience preferred, excellent communication, and mentoring ability.
ATPG, Automatic Test Equipment (ATE), EDA
1mo
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Senior DFT Engineer
Santa Clara, California, United States
$168k-$311k/yr HybridFull Time
6+ YOEMS/PhD or equivalent experience in Electrical Engineering, 6+ years DFT experience, deep knowledge of DFT/ATPG/EDA/ATE tools, strong communication and mentoring skills.
ATPG, EDA, ATE, CAD
1mo
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DFT Engineer, Google Cloud
Sunnyvale, California, United States
$138k-$198k/yr OnsiteFull Time
3+ YOEBachelor's degree or equivalent experience, 3+ years in DFT/ATPG/verification for SoCs, familiarity with ATE/MBIST/JTAG, EM/EDA tool experience, strong communication and critical thinking.
ATE, MBIST, JTAG, iJTAG, Design Compiler, DFT Max, Tessent, TestKompress
2mo
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DFT Engineer
Richardson, Texas, United States
$106k-$184k/yr OnsiteFull Time
4+ YOEBachelor’s or Master’s in Electrical/Computer Engineering or related field; 4+ years DFT on SoCs; ATPG, MBIST, LBIST; EDA tools; scripting; test optimization; cross-functional collaboration.
Synopsys TestMAX, Cadence Modus, Mentor Tessent, Python, Perl, TCL
2mo
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DFT Engineer
Santa Clara, California, United States
$60k-$149k/yr OnsiteFull Time
5+ YOEHands-on experience in Scan, ATPG, MBIST, Boundary Scan/JTAG and VLSI HVL verification; experience in at least 2 DFT areas; 5+ years experience preferred (5-8 years listed).
Scan, ATPG, GLS, MBIST, Boundary Scan (BSCAN, JTAG), VLSI HVL Verification
1mo
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CPU DFT Engineer
Santa Clara, California, United States
$142k-$213k/yr OnsiteFull Time
5+ YOEDegree in EE/CE/CS (advanced degrees acceptable); senior-level ASIC/DFT experience (multi-year); Verilog/VHDL, Mentor Tessent, ASIC test/DFT/debug, SOC verification, TCL/Perl/Python/Shell scripting.
Verilog, VHDL, Mentor Tessent, TCL, Perl, Python, Shell
1mo
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Principal DFT Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years DFT implementation and verification experience including scan architectures, JTAG, memory MBIST, ATPG; Verilog/VHDL RTL knowledge; ability to handle RTL DFT changes, analyze ATPG/DRC reports, and support test pattern bring-up.
RTL, MBIST, ATPG, JTAG, TAP, ATE, Verilog, VHDL, SDF
2mo
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DFT Engineer
Richardson, Texas, United States
$106k-$184k/yr OnsiteFull Time
4+ YOEBSc or MSc in EE/CE or related field, 4+ years DFT experience on SoCs (ATPG, MBIST, LBIST, scan), proficiency with Synopsys TestMAX/Cadence Modus/Mentor Tessent, scripting (Python, Perl, TCL), strong analytical and communication skills.
Synopsys TestMAX, Cadence Modus, Mentor Tessent, Python, Perl, TCL, ATPG, MBIST, LBIST
2w
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DFT Design Engineering Director
San Jose, California, United States
$230k-$265k/yr OnsiteFull Time
12+ YOE5+ MgmtMS/PhD in EE/CE or related, 12+ years DFT experience (5+ years leadership), deep expertise in 2.5D/3D packaging DFT, proven tape-out and production ramp experience, familiarity with DFT EDA tools and ATE platforms.
COSMOS, Synopsys DFT Compiler, TetraMAX, DFTMAX, Mentor Tessent, Advantest, Teradyne
2mo
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Senior DFT Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
8+ YOESenior DFT Engineer with 8+ years in design-for-test for complex digital ASICs/SoCs; expertise with DFT tools; RTL/ASIC test optimization.
Verilog, SystemVerilog, UVM, VHDL, Tcl, Python, Perl, Synopsys DFT Compiler, Tessent, DFTMAX, MBIST, JTAG, ATPG
3mo
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DFT Intern
San Jose, California, United States
OnsiteInternship, Full Time
Pursuing Bachelor's, Master's, or PhD in EE/CE or related field; familiarity with Verilog/SystemVerilog; exposure to ASIC/SoC concepts; digital logic; ASIC design flow; scripting in Python/Tcl; interest in transformers/AI.
Verilog, SystemVerilog, Python, Tcl, DFT Tools, Tessent
4d
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DFT Staff Engineer
Santa Clara, California, United States
HybridFull Time
Experience with DFT/ATPG and scan compression, Verilog logic design, post-silicon debug, Linux and scripting (Perl,Tcl); Bachelor's in EE/CE required, Master’s preferred.
ATPG, Tessent Scan/ATPG, Verilog, Linux, Perl, Tcl
2mo
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Principal Test Engineer/DFT Architect
Austin, Texas, United States
OnsiteFull Time
12+ YOEDefine product-level test/DFT strategy; lead cross-functional DFT efforts; mentor engineers; 12+ years in semiconductor test/DFT; strong ATE experience.
ATE, DFT, signal measurement, scripting, Python, MATLAB, SQL
4d
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DFT Implementation Engineer
Austin, Texas, United States
$142k-$200k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE,5+ years DFT/SoC design experience, RTL design (Verilog/VHDL/SystemVerilog), ATPG/scan/MBIST experience, Tessent and industry DFT tool knowledge, scripting (TCL/Perl/Python).
Tessent Shell, SSN, Tessent Fast IO, ISTK, Siemens EDA (Mentor) Tessent, Synopsys DFT Compiler, Cadence Modus, ATPG, MBIST, Verilog, VHDL, SystemVerilog, TCL, Perl, Python, UPF
3w
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Sr. Staff Engineer - DFT
Austin, Texas, United States
OnsiteFull Time
10+ YOEBS/MS in ECE/EE with 10+ years DFT experience; skilled in scan, scan compression, boundary scan, MBIST, low-power DFT, ATPG and RTL; experience with Tessent MBIST flow, Cadence Genus/Modus, and scripting (Tcl, Perl, Python).
Cadence Genus, Modus, Tessent, Tcl, Perl, Python
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