3mo
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Digital Design Engineer
Saratoga, California, United States
$150k-$250k/yr OnsiteFull Time
Design digital avionics boards, high-speed interfaces, clocking, power budgeting, radiation-tolerant design; collaborate with FPGA teams; board bring-up and design reviews.
Altium Designer, HyperLynx SI, HyperLynx PI, Full-Wave, SPICE-based circuit simulation, FPGA vendor toolchains
2mo
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Principal Digital Design Engineer / Chip Lead
Minneapolis or Boise or Folsom or Richardson or San Jose
$206k-$410k/yr OnsiteFull Time
10+ YOE10+ years in digital/ASIC design with chip/design lead ownership; SystemVerilog RTL; synthesis/timing tools; cross-team integration leadership.
SystemVerilog, DC, Genus, PrimeTime, Tempus
2mo
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DMTS Digital Design Engineer / Chip Lead
Minneapolis or Boise or Folsom or Richardson or San Jose
$206k-$410k/yr OnsiteFull Time
10+ YOE10+ years ASIC/digital design experience with prior tape-out; BS/MS/PhD in EE/CE or related; expert SystemVerilog; synthesis (Design Compiler/Genus), static timing analysis (PrimeTime/Tempus), RTL simulation (VCS/Xcelium), CDC tools; chip architecture and IP integration experience.
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Tempus, VCS, Xcelium, Verdi, DVE, SpyGlass, JasperGold
2mo
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Member of Technical Staff, AI‑Optimized Memory Digital Design Engineer / Microarchitect
Folsom or Richardson
$177k-$309k/yr OnsiteFull Time
5+ YOESenior digital/microarchitecture engineer with 5+ years delivering silicon-demonstrated memory/SoC designs; SystemVerilog RTL design, synthesis and PPA optimization; experience with C/C++ or Python; strong memory system architecture knowledge.
SystemVerilog, C/C++, Python
3mo
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Staff Design Engineer, Pathfinding
Folsom or Boise or San Jose
$116k-$246k/yr OnsiteFull Time
5+ YOE5+ years IC design experience (mixed-signal/analog/digital) for memory technologies; BSEE/MSEE in Electrical Engineering; SPICE and Verilog modeling; regulator/charge pump/oscillator/bandgap experience; strong communication skills.
SPICE, Verilog, UNIX, Cadence, SPF
2mo
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Principal Analog Design Engineer — Mixed-Signal PHY (Clocking / High-Speed I/O)
Boise or Folsom or Richardson or San Jose
$159k-$347k/yr OnsiteFull Time
10+ YOE10+ years analog/mixed-signal IC design; PLL/DLL/clocking; transistor-level simulations; analog-digital interfaces; lab data correlation
HSpice
2mo
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SMTS Analog Design Engineer, Mixed-Signal PHY (Clocking & High-Speed I/O)
Boise or Folsom or Richardson or San Jose
$159k-$347k/yr OnsiteFull Time
10+ YOEBS/MS/PhD in EE; 10+ years analog/mixed-signal IC design with tape-out; deep clocking (PLL/DLL/CDR) expertise; transistor-level simulation with HSpice; strong jitter analysis and analog-digital interface experience.
HSpice, Verilog-AMS, Real-number modeling (RNM)
2mo
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Member of Technical Staff, AI‑Optimized Memory Digital Design Engineer / Microarchitect
Folsom or Richardson
$177k-$309k/yr OnsiteFull Time
5+ YOE5+ years of digital design and memory systems experience; strong microarchitecture knowledge; proficiency in SystemVerilog, C/C++, Python; ability to drive data-driven architectural decisions.
SystemVerilog, C/C++, Python, Synthesis tools
2mo
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Senior Electrical Engineer
Irving or Bronx or Sacramento or Dallas
$125k-$135k/yr OnsiteFull Time
10+ YOE10+ years electrical engineering; analog/digital circuit design; up to 600VAC; PCB layout; Ethernet/CAN/RS232; elevator domain knowledge.
Altium, Embedded C, FPGA, CAN, Ethernet, RS232/422
1mo
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DSP Specialist FAE (Field Applications Engineer) – West Region
Sacramento, California, United States
$159k-$230k/yr RemoteFull Time
10+ YOE10+ years FPGA digital design and DSP experience, Bachelor's degree in a STEM field, proficiency with Quartus/Vivado, DSP Builder/System Generator/OneAPI, MATLAB/Simulink, Python or C/C++, and willingness to travel; eligibility for required U.S. export authorizations.
Quartus, Vivado, DSP Builder, System Generator, OneAPI, MATLAB, Simulink, Python, C/C++
1mo
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Member of Technical Staff, AI-optimized Physical/Platform Architect
Folsom, California, United States
$177k-$309k/yr OnsiteFull Time
Experience in analog/digital design, high-performance memory systems (e.g., HBM), thermal modeling (FloTherm), 2.5D/3D IO architecture, and power delivery/thermal architectures; strong cross-domain analysis and communication skills.
FloTherm