9 digital design engineer jobs at 2 companies in Placerville, CA
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MTS, AI Optimized Memory Digital Design Engineer
Folsom or Richardson
$175k-$309k/yr OnsiteFull Time
Bachelor's in CS/CE/EE, strong digital design and microarchitecture experience, SystemVerilog proficiency, synthesis and PPA optimization experience, and programming in C/C++/Python.
SystemVerilog, C, C++, Python, Agentic AI
2mo
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Member of Technical Staff, AI‑Optimized Memory Digital Design Engineer / Microarchitect
Folsom or Richardson
$177k-$309k/yr OnsiteFull Time
5+ YOESenior digital/microarchitecture engineer with 5+ years delivering silicon-demonstrated memory/SoC designs; SystemVerilog RTL design, synthesis and PPA optimization; experience with C/C++ or Python; strong memory system architecture knowledge.
SystemVerilog, C/C++, Python
3d
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MTS, AI Optimized Memory Digital Design Engineer
Folsom or Richardson
$175k-$309k/yr OnsiteFull Time
Bachelor's in CS/CE/EE, strong digital design and microarchitecture experience, SystemVerilog and programming (C/C++/Python) proficiency, synthesis and PPA experience, and experience delivering silicon-proven designs.
SystemVerilog, C, C++, Python, Agentic AI
4d
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Staff Design and Verification Engineer, Pathfinding
Folsom or Boise or San Jose
$116k-$246k/yr OnsiteFull Time
4+ YOE4+ years verification experience in digital/analog/mixed-signal, expertise in Verilog, FastSpice, co-simulation, SPICE, UNIX and Cadence; strong circuit and semiconductor physics knowledge and problem-solving skills.
Verilog, FastSpice, UNIX, Cadence, SPICE
4d
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Staff Design and Verification Engineer, Pathfinding
Folsom or Boise or San Jose
$116k-$246k/yr OnsiteFull Time
4+ YOE4+ years verification experience in digital/analog/mixed-signal; expertise in Verilog, SPICE/FastSpice, co-simulation, real-number modeling; proficiency with UNIX and Cadence; BS/MS/PhD in electrical or related field or equivalent experience.
Verilog, FastSpice, SPICE, UNIX, Cadence, Artificial Intelligence (AI)
2mo
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SMTS Analog Design Engineer, Mixed-Signal PHY (Clocking & High-Speed I/O)
Boise or Folsom or Richardson or San Jose
$159k-$347k/yr OnsiteFull Time
10+ YOEBS/MS/PhD in EE; 10+ years analog/mixed-signal IC design with tape-out; deep clocking (PLL/DLL/CDR) expertise; transistor-level simulation with HSpice; strong jitter analysis and analog-digital interface experience.
HSpice, Verilog-AMS, Real-number modeling (RNM)
2mo
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Member of Technical Staff, AI‑Optimized Memory Digital Design Engineer / Microarchitect
Folsom or Richardson
$177k-$309k/yr OnsiteFull Time
5+ YOE5+ years of digital design and memory systems experience; strong microarchitecture knowledge; proficiency in SystemVerilog, C/C++, Python; ability to drive data-driven architectural decisions.
SystemVerilog, C/C++, Python, Synthesis tools
2mo
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Senior Electrical Engineer
Irving or Bronx or Sacramento or Dallas
$125k-$135k/yr OnsiteFull Time
10+ YOE10+ years electrical engineering; analog/digital circuit design; up to 600VAC; PCB layout; Ethernet/CAN/RS232; elevator domain knowledge.
Altium, Embedded C, FPGA, CAN, Ethernet, RS232/422
1mo
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Member of Technical Staff, AI-optimized Physical/Platform Architect
Folsom, California, United States
$177k-$309k/yr OnsiteFull Time
Experience in analog/digital design, high-performance memory systems (e.g., HBM), thermal modeling (FloTherm), 2.5D/3D IO architecture, and power delivery/thermal architectures; strong cross-domain analysis and communication skills.
FloTherm