2mo
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Staff UI UX Designer
San Jose, California, United States
$170k-$215k/yr OnsiteFull Time
5+ YOE5+ years in senior or staff-level digital product design; SaaS/enterprise UI; collaborative; proficient in design tools; experience with AI/data-driven environments; degree in Design or related field.
Figma, Adobe, Claude
1w
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Digital Design Engineer
San Jose, California, United States
$130k-$200k/yr OnsiteFull Time
5+ YOEBS/MS/PhD in EE/CE,5+ years digital RTL design experience,SystemVerilog proficiency,ASIC flow and EDA tool experience,high-speed SerDes/DSP knowledge,Python/MATLAB/C++ familiarity.
System Verilog, Synopsys, Cadence, Siemens, Python, MATLAB, C++
2mo
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Principal Digital Design Engineer / Chip Lead
Minneapolis or Boise or Folsom or Richardson or San Jose
$206k-$410k/yr OnsiteFull Time
10+ YOE10+ years in digital/ASIC design with chip/design lead ownership; SystemVerilog RTL; synthesis/timing tools; cross-team integration leadership.
SystemVerilog, DC, Genus, PrimeTime, Tempus
1mo
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Principal Digital Design Engineer
San Jose, California, United States
OnsiteFull Time
5+ YOEBachelor’s or Master’s in Electrical/Computer Engineering or related field; 5-10 years in digital design for high-speed DSP data paths; SystemVerilog coding; experience with Synthesis, Lint, CDC, PrimeTime; RTL delivery; full design cycle; timing/area/power optimization; silicon issue resolution
SystemVerilog, EDA tools, Synthesis, Lint, CDC, PrimeTime
1w
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Image Sensor Digital Design Lead - PICO - SanJose
San Jose, California, United States
OnsiteFull Time
5+ YOEMaster's in EE/CS, 5+ years digital design lead experience, front-end digital design and EDA expertise, strong image sensor architecture and interface knowledge (I2C, MIPI).
EDA tools, RTL, I2C, MIPI
1mo
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Senior Engineer, Digital Design Engineering
San Jose, California, United States
$157k-$202k/yr HybridFull Time
2+ YOEMaster's in EE/CE/CS or related, 2+ years digital/mixed-signal design and verification experience, expertise in RTL, Lint, CDC, Verilog/System Verilog, Cadence or Synopsis tools, simulation, synthesis, and ASIC flow.
Cadence, Synopsis, Verilog, System Verilog, RTL, Lint, CDC
1mo
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Digital Design Engineer - New College Grad
San Jose, California, United States
$99k-$183k/yr HybridFull Time
Master's degree in EE or related field; experience with RTL coding, Verilog models, and analog/digital design; test support and chip bring-up; strong communication and team skills.
Verilog, RTL, Simulations, I2C, SPI, AHB, APB, Bench testing, ATE testing
1w
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SoC Digital Design Engineer, Multimedia Lab
San Jose, California, United States
$156k-$317k/yr OnsiteFull Time
1+ YOEBachelor's in EE/CS or related, 1+ years front-end digital design, mastery of Verilog/SystemVerilog, experience with front-end EDA tools, scripting (Python/Perl/Tcl/Makefile).
Verilog, SystemVerilog, Spyglass, Design Compiler, PrimeTime, Python, Perl, Tcl, Makefile, UPF, SDC, STA, FPGA, ASIC
2mo
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DMTS Digital Design Engineer / Chip Lead
Minneapolis or Boise or Folsom or Richardson or San Jose
$206k-$410k/yr OnsiteFull Time
10+ YOE10+ years ASIC/digital design experience with prior tape-out; BS/MS/PhD in EE/CE or related; expert SystemVerilog; synthesis (Design Compiler/Genus), static timing analysis (PrimeTime/Tempus), RTL simulation (VCS/Xcelium), CDC tools; chip architecture and IP integration experience.
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Tempus, VCS, Xcelium, Verdi, DVE, SpyGlass, JasperGold
1mo
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ASIC Digital Design, Sr Staff Engineer
Noida or Bangalore or San Jose
OnsiteFull Time
8+ YOEBSEE/MSEE with 8+ years ASIC digital design experience; expertise in UCIe/PCIe/DDR/CXL/USB, SystemVerilog/Verilog, synthesis, CDC, formal, STA, Fusion Compiler, Perforce, and scripting (Perl/Shell).
SystemVerilog, Verilog, Fusion Compiler, Perforce, Perl, Shell
1d
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Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEBSEE required; 8+ years experience in SoC integration with RTL design in advanced nodes, SystemVerilog proficiency, PPA/CDC/RDC and low-power design knowledge; EMR not mentioned.
SystemVerilog
1w
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SoC Interconnect and Fabric RTL Designer
San Jose, California, United States
HybridFull Time
8+ YOEBS/MS in EE/Computer Engineering, 8+ years digital IC design with 4+ years owning on-chip interconnect/NoC or fabric architecture; strong SystemVerilog, AXI/CHI/NoC, CDC, integration, and register-map experience.
AXI4, AXI4-Lite, AXI-Stream, CHI, AMBA CHI, ACE, NoC, SystemVerilog, SystemRDL, IP-XACT
2mo
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MTS Digital Design Engineer
San Jose, California, United States
OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
17+ YOEBS EE with 17+ years or MS with 15+ years; strong RTL/Verilog; ASIC/mixed-signal ICs; power management; leadership and cross-functional communication.
Verilog, SystemVerilog, TCL, Python, Perl, XML
16h
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Principal Digital Design Engineer
San Jose, California, United States
$190k-$240k/yr HybridFull Time
8+ YOEMS/PhD EE with 8+ years or BS EE with 12+ years; SOC architecture experience, bus/interface protocols, embedded memory knowledge, RTL/DFT/synthesis flow, silicon bring-up, strong communication and team skills.
AHB, APB, AXI, USB, I2C, I3C, SPI, UART, SRAM, OTP, MTP, EE/Flash, DDR DRAM, Flash
1w
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Graduate- Senior Engineer Digital IC Design
San Jose, California, United States
$127k-$174k/yr HybridFull Time
0+ YOEBachelor's degree in CS/EE/CE or related,0-2 years experience,knowledge of Verilog/System Verilog and digital frontend flows,RTL coding,verification/debugging,emphasis on automotive safety;Python/Perl preferred;must be legally authorized to work in the US.
Verilog, System Verilog, Python, Perl
1mo
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Principal RF Designer and Architect (Richardson, TX, US, 75081)
Richardson or San Jose
$170k-$222k/yr OnsiteFull Time
6+ YOEMSEE required (PhD preferred); 6+ years in RF/microwave or defense; expertise in RF, analog/digital circuit design, PCB layout, Spice simulations, power management, ADC/DAC, and hardware test equipment.
Spice, AWGs, signal analyzers, mixed signal oscilloscopes
1d
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Digital Design Specialist: Structural Engineering
San Jose, California, United States
$74k-$99k/yr HybridFull Time
4+ YOE4+ years experience in structural drafting/BIM, proficiency in CAD and Revit, strong communication, attention to detail, ability to produce construction documentation.
CAD, Revit, BIM
3w
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Sr. Staff/Staff Engineer, Digital Design
San Diego or San Jose
OnsiteFull Time
Deep RTL/SystemVerilog expertise, SoC architecture knowledge, familiarity with AXI/AHB/APB/OBI, multi-clock/multi-power-domain and timing closure experience, skills with SystemVerilog, Python, Tcl, UPF, and security technologies (Arm TrustZone, Secure Boot, PSA Level 2+); MS/PhD preferred.
SystemVerilog, Python, Tcl, UPF, AXI, AHB, APB, OBI, Arm TrustZone
1mo
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Principal Engineer - Digital ASIC Design
San Jose, California, United States
$70k-$163k/yr OnsiteFull Time
10+ YOE10+ years ASIC/FPGA digital design; SystemVerilog; Cadence/Synopsys front-end; PHY/Serdes knowledge; post-silicon validation; travel up to 25%.
System Verilog, Cadence Tools, Synopsys Tools, VCS, SpyGlass, Design Compiler, PrimeTime, Lab equipment
6d
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Sr. / Staff ASIC Digital Design Engineer
San Jose, California, United States
OnsiteFull Time
6+ YOEExpertise in DFT, synthesis, power and timing analysis; tapeout experience; scripting (tcl/perl/python/shell); UPF and STA; Bachelors+8 years or Masters+6 years in engineering.
Synopsys, Siemens Tessent, PT, DC, VCLP, Formality, LEC, PrimeClosure, PrimePower, VCS, VC-spyglass-dft, Tetramax, Tessent, UPF, UNIX, Linux, tcl, perl, python, shell
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