1w
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Director, Digital Design & Verification
Chandler, Arizona, United States
OnsiteFull Time
Proven leader in digital IC design and verification for mixed-signal SoCs with expertise in RTL, verification methodologies (UVM, formal, AMS/DMS), architecture, and team building.
SystemVerilog, UVM, Formal, AMS/DMS, RTL, STA, DFT
6d
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FPGA Digital Engineer - 2
Chandler, Arizona, United States
$87k-$131k/yr OnsiteFull Time
2+ YOEBachelor's in EE/CE plus 2 years (or Master's), ability to obtain DoD Secret clearance, FPGA (VHDL/Verilog) experience, Vivado and simulation tool familiarity, and digital interface verification experience.
VHDL, Verilog, AMD Xilinx FPGAs, Vivado IDE, Questa, ModelSim, Vitis Unified IDE, C, C++, OSVVM, UVM
6d
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Principal FPGA Digital Engineer - 3
Chandler, Arizona, United States
$108k-$162k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE (or MS/PhD) with relevant FPGA/SoC design experience, expertise in VHDL/Verilog and Xilinx toolflow, static timing analysis, bus interfaces, simulation/verification, and ability to obtain DoD Secret clearance.
VHDL, Verilog, AMD Xilinx FPGAs, Vivado IDE, Vitis Unified IDE, Questa/ModelSim, OSVVM, UVM, AXI4, Ethernet, PCIe, UART, SDLC, DDR3, DDR4, DDR5, logic analyzer, oscilloscope, C, C++
3mo
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Principal Engineer - Digital Design
Chandler, Arizona, United States
OnsiteFull Time
10+ YOEBachelors with 10+ years in digital design; RTL coding/verification; USB/Ethernet PHY knowledge; Verilog/SystemVerilog; UVM/VMM a plus; ASIC flow; CAD tools; timing; scripting.
Verilog, SystemVerilog, UVM, Questa, Design Compiler, Formality, Spyglass, Crossing Clock domain checking, lint, stuck-at, At-Speed scan, Scripting (C, TCL, Perl, Awk, UNIX shell), CVS, Perforce, DesignSync
1mo
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Senior Electrical Engineer (AZ, Scottsdale)
Scottsdale, Arizona, United States
OnsiteFull Time
Design, analyze, test, and troubleshoot analog, digital, mixed-signal, and embedded electronic systems; support system integration, verification/validation, manufacturing transfer, and sustaining engineering for medical devices.
3w
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Senior DfT Engineer
Chandler, Arizona, United States
HybridFull Time
3+ YOEMaster's (MSEE) in relevant fields, 3+ years DfT/digital design experience, strong RTL coding and verification skills, Verilog/SystemVerilog proficiency, problem solving and communication skills.
Verilog, SystemVerilog
2w
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Avionics Hardware Engineer II - Lunar Permanence
Seattle or Phoenix or Denver or Los Angeles
$98k-$150k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
2+ YOEBS in Electrical/Computer Engineering,2+ years avionics or electronics hardware design experience; analog/digital/mixed-signal design, part selection, signal integrity, and board-level test/verification.
TCL, Python, Linux shell, Windows batch, C, C++, MATLAB, Simulink, HSPICE, HFSS
1mo
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Memory Circuit Design Engineer
Hillsboro or Santa Clara or Austin or Phoenix
$122k-$232k/yr HybridFull Time
4+ YOEMaster's in EE/CE + 4+ years' experience or PhD; experience designing/characterizing memory circuits (SRAM/ROM/Register Files), PPA optimization, custom digital design, simulation, layout, verification, and knowledge of EDA tools.
EDA tools