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Digital Verification Engineer
Santa Clara, California, United States
OnsiteFull Time
3+ YOE3+ years digital verification experience for FPGA/ASIC, proficiency in Verilog/SystemVerilog, experience with Modelsim/Questasim or NC-Verilog, BS/MS in EE/CE, strong coverage and assertion skills.
Verilog, SystemVerilog, Modelsim, Questasim, NC-Verilog, UVM
2mo
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Digital Verification Engineer Expert
New York, United States
$147k-$235k/yr OnsiteFull Time
Bachelor's degree in Electrical/Computer Engineering or Computer Science; expert in SystemVerilog, UVM, SVA; simulators; Digital verification and coverage strategies; able to lead or mentor; strong English communication.
SystemVerilog, UVM, SVA, Simulators, Python, Make, Bash, C, C++, Jira, Git, Formal verification, DSP, Forward Error Correction
1mo
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Digital Design Verification Engineer
Bristol or Austin
£125k/yr OnsiteFull Time
5+ YOE5+ years in digital verification for high-performance ASICs/SoCs; strong SystemVerilog, SVA, UVM, Cocotb, formal verification, CDC/RDC, and algorithm modelling (MATLAB/Simulink or Python/NumPy) skills; experience with high-speed IP (SerDes, DDR/HBM, PCIe).
SystemVerilog, UVM, SVA, CocoTB, MATLAB/Simulink, Python, NumPy, Jasper, FPGA, RTL simulation, formal verification, linting, CDC/RDC, STA, UPF, CPF, gate-level simulation
1mo
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Principal Digital Verification Engineer
Plano, Texas, United States
OnsiteFull Time
8+ YOE8+ years in verification; MS in Electrical/Computer Engineering or equivalent; BS with 10+ years; UVM and SystemVerilog experience; DDR5 verification
UVM, SystemVerilog, Verilog, DDR5
1mo
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Principal/ Sr. Principal Digital Verification Engineer
San Diego, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOEUS citizen able to obtain Secret clearance. Bachelor’s in EE or STEM required. 5+ years digital verification experience (Principal) or 8+ years (Sr. Principal). VHDL, FPGA verification, Siemens Questa, verification planning, and simulation/debug skills.
VHDL, FPGA, Siemens Questa Simulator, OSVVM, Perl, TCL, Bash, Makefile, Linux, Siemens Lint, Siemens Inspect, Siemens CDC
1mo
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Principal/ Sr. Principal Digital Verification Engineer
San Diego, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOEBachelor's in EE or other STEM; 5+ (Principal) or 8+ (Sr Principal) years digital verification experience; VHDL and FPGA verification; Siemens Questa Simulator; US citizenship and ability to obtain Secret clearance.
VHDL, Siemens Questa Simulator, OSVVM, Perl, TCL, Bash, Makefile, Siemens Lint, Siemens Inspect, Siemens CDC
1mo
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Digital Design Verification Engineer | Precision ADC
Tucson, Arizona, United States
OnsiteFull Time
2+ YOEBachelor's degree in Electrical or Computer Engineering; 2+ years in digital design or verification; SystemVerilog/hardware simulation experience; digital logic fundamentals; systematic problem solving; strong communication and teamwork.
SystemVerilog, UVM, Hardware simulation, VCS, Xcelium, Questa, Python, Perl
1mo
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Principal Digital IP Verification Engineer
Austin, Texas, United States
HybridFull Time
3+ YOEExpertise in digital IP verification including SystemVerilog, UVM/OVM, formal methods, scripting (Python/Perl), low-power verification (CPF/UPF), and protocol knowledge (DDR, PCIe, AMBA). Requires advanced degree/experience per role.
DDR, PCIe, AMBA, CHI, ACE, AXI, Verilog, SystemVerilog, VHDL, OVM, UVM, SystemVerilog Assertions (SVA), formal verification, CPF, UPF, Python, Perl, UNIX, Linux, HAPS, Palladium, Zebu, AI/LLM
2mo
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Digital - Principal Digital Verification Engineer
Vancouver or California
OnsiteFull Time
15+ YOEBS in Electrical Engineering; 15+ years of experience; strong UVM/SystemVerilog expertise; regression management; connectivity IPs; start-up experience.
SystemVerilog, UVM, DPI, CI/CD, scripting language
1w
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Digital Verification Engineer Lead (MTD, Tualatin, OR)
Tualatin, Oregon, United States
$155k-$248k/yr OnsiteFull Time
10+ YOE10+ years verification experience with System Verilog/UVM, verification planning, testbench architecture, scripting, source control, and leading cross-site verification teams.
System Verilog, UVM, Makefiles, shell, TCL, Perl, Python, clearcase, git, svn, GVP, Ethernet, PCIe, AXI, MIPI, DRAM, FLASH
1mo
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Digital Design Verification, Principal Engineer-17853
Austin, Texas, United States
$166k-$249k/yr OnsiteFull Time
12+ YOE12+ years IP/SoC verification experience, proficiency with Synopsys verification tools, agentic AI exposure, scripting in SystemVerilog/UVM/Tcl/Python, and BS/MS in electrical/electronics/computer engineering.
VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), VIPs, Cursor, Microsoft VS Code co-pilot, SystemVerilog, UVM, Tcl, Python
1w
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Digital Verification Engineer (MTD, San Jose, CA)
San Jose, California, United States
$135k-$217k/yr OnsiteFull Time
Teradyne Inc: A global test and automation specialist providing manufacturing automation and test technology to ensure product quality.
6+ YOE6+ years verification experience (MS) or 8+ years (BS); experience with SystemVerilog/UVM, EDA tools, verification IP, industry protocols, source control and verification test planning.
Cadence ePlanner, Cadence Xcelium, Simvision, System Verilog, UVM, AXI, PCIe, DDR3, DDR4, DDR5, clearcase, git, svn, Make, shell, TCL, Perl, Python
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Digital Verification Engineer - Weapon Subsystems 2
Albuquerque or Livermore or United States
$122k-$238k/yr HybridFull Time, Temporary
Bachelor's in relevant discipline (or equivalent experience), ability to obtain DOE Q-level clearance, expertise in formal verification, VHDL/Verilog/SVA proficiency, strong analytical and written communication skills.
VHDL, Verilog, SystemVerilog Assertions (SVA)
1mo
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Digital Verification Engineer - Weapon Subsystems 2
Livermore or California or New Mexico or United States
$122k-$238k/yr HybridFull Time, Temporary
Bachelor's degree or equivalent, ability to obtain DOE Q-level (Top Secret) clearance, several years applying formal verification to FPGA/ASIC, proficiency with VHDL, Verilog, and SystemVerilog Assertions (SVA), strong analytical and written communication skills.
VHDL, Verilog, SystemVerilog Assertions (SVA)
3mo
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Senior Digital Design Verification Engineer - Hardware
Santa Clara, California, United States
$136k-$265k/yr OnsiteFull Time
5+ YOE5+ years verification experience; Bachelors or Masters in EE/CS/CE (or equivalent); expertise in SystemVerilog, UVM/VMM, random stimulus, functional coverage, and assertion-based verification; simulation/debug tools experience.
SystemVerilog, UVM, VMM, Perl, Python, C/C++
3mo
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Design Verification Engineer
Austin, Texas, United States
OnsiteFull Time
10+ YOEBS with 10+ years in digital verification; SystemVerilog, UVM, Python/Perl; SOC/IP verification experience; strong communication.
SystemVerilog, UVM, Python, Perl, C/C++, Digital design, Scripting
1mo
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Sr. Staff Engineer - Digital Design Verification
Austin, Texas, United States
OnsiteFull Time
8+ YOEBSEE or MSEE with 8+ years verifying complex SoC digital designs using SystemVerilog/UVM and C/C++; proven tape-outs, SoC-level verification, and strong collaboration and debugging skills.
SystemVerilog, UVM, Verilog, C/C++, Python, Perl, Makefile
3mo
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Senior Digital Mixed-Signal (DMS) Verification Engineer
Mendota Heights or Broomfield
$108k-$173k/yr OnsiteFull Time
5+ YOE5+ years in digital verification of mixed-signal ASICs/SoCs; UVM/OVM; analog/digital boundary expertise; leadership; Bachelors in EE/CE/CS with 8+ yrs experience or Masters with 6+ yrs; English communication.
UVM, OVM, SystemVerilog, SystemVerilog Assertions, scripting, automation tooling
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Principal Verification Engineer I
Westminster, Colorado, United States
$160k-$190k/yr OnsiteFull Time
9+ YOEBS in CS/EE/CE (MS preferred), 9+ years verification and automation experience, expert in FPGA/digital verification techniques and CI infrastructure.
VHDL, Verilog, SystemVerilog, C/C++, SystemC, UVM, UVMf, DPI-C, TLM, QEMU, VIP, MATLAB, Python, Linux, Xilinx, CI, HIL
1mo
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Principal Engineer Pre-Silicon Digital Verification
Andover or Austin or El Segundo
$146k-$201k/yr OnsiteFull Time
Expertise in ASIC design and digital/mixed-signal verification, System Verilog and UVM, scripting (Unix/Linux shell, Perl, Python), testbench and coverage development, formal verification and analog behavioral modeling.
System Verilog, UVM, Unix/Linux shell, Perl, Python
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