51 engineer digital design engineering jobs at 23 companies in Cave Creek, AZ
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Principal Engineer, Digital Design Engineering
Chandler or Wilmington
$152k-$227k/yr OnsiteFull Time
12+ YOE12+ years in digital design engineering with SoC architecture expertise, multi-domain technical mastery, ability to define technical strategy, lead architecture, drive innovation, mentor engineers, and engage with customers and industry.
1w
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Senior Digital Design Engineer
Vancouver or Chandler or San Francisco
$150k-$200k/yr HybridFull Time
6+ YOEBachelor's or master's degree in electrical or computer engineering, 6+ years of digital IC design experience, and hands-on Verilog or SystemVerilog RTL development for complex SoCs or ASICs.
Verilog, SystemVerilog, Synopsys, Cadence, SDC, UPF, CPF
2w
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Sr Digital Design Engineer
Chandler, Arizona, United States
OnsiteFull Time
10+ YOEM.S. in electrical, computer, or related engineering; 10+ years in digital IC design; Verilog/SystemVerilog, EDA tools, synthesis, timing analysis, verification, UVM, and technical leadership experience.
Verilog, SystemVerilog, UVM, Cadence, Synopsys, Siemens EDA
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Senior Digital Design Engineer
Scottsdale, Arizona, United States
HybridFull Time
Bachelor’s degree in electrical engineering or related STEM field plus 5+ years’ experience, or master’s degree plus 3 years. TS/SCI clearance eligibility, U.S. citizenship, PCB and digital design expertise required.
Allegro, Mentor, FPGAs, System-on-Chips
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Staff Digital Design Engineer
Chandler, Arizona, United States
HybridFull Time
11+ YOE>10 years digital design experience, degree in EE/CE/CS or related, fluent Verilog/SystemVerilog, ASIC methodology knowledge, Lint/CDC/RDC experience, RTL and gate-level debug, English proficiency, travel readiness.
Verilog, SystemVerilog, Lint, CDC, RDC, UPF, UVM, AMBA, I2C, STA
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Senior Digital Design Engineer
Scottsdale, Arizona, United States
$119k-$131k/yr HybridFull Time
5+ YOEBachelor's in EE or related plus 5+ years (or Master's+3). Must obtain TS/SCI clearance, US citizenship required. Experience with schematic capture, multilayer PCB design, signal integrity, microprocessors/FPGAs, and technical leadership.
Allegro, Mentor
2d
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Intern- Engineering (Design)
Chandler, Arizona, United States
OnsitePart Time, Internship
Current Electrical or Computer Engineering student at senior or postgraduate level with digital design coursework and Verilog/SystemVerilog projects; scripting with TCL, Python, or Perl preferred.
Verilog, SystemVerilog, TCL, Python, Perl
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Lead, Digital Design Engineer (41438)
Londonderry or Tempe
OnsiteFull Time
9+ YOE9+ years firmware/FPGA (VHDL/Verilog) experience, experience with image/video processing, EM interfaces, test equipment, and translating system into firmware requirements.
VHDL, Verilog, Microchip, Xilinx, Altera (Intel), OrCAD, PSpice, Cadence Allegro, Git, Jira, Jenkins, DOORS, ModelSim, Oscilloscope, Logic Analyzer, Spectrum Analyzer
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Principal Electrical Design Engineer
Phoenix or Huntsville or Cypress or Andover or Chantilly or Alpharetta or Torrance or Gulf Breeze
OnsiteFull Time
6+ YOEBS in Electrical/Computer Engineering; 6+ years embedded hardware design; high-speed digital design; lead and mentor engineers; travel; security clearance awareness
Cadence Allegro, Mentor, JAMA, DOORS, JIRA, Confluence, FMEA/DFM/DFT
2d
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Director Engineering, Systems & Digital
Phoenix or Montreal or Vancouver
OnsiteFull Time
20+ YOEDegree-qualified engineering leader with 20+ years in engineering design across minerals processing, oil and gas, chemical or related sectors, plus senior leadership and EPCM experience.
BIM, CDE, AI
1w
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Hardware Design Engineer
Tempe or San Jose or San Francisco or New York City
$133k-$210k/yr OnsiteFull Time
4+ YOEBachelor's degree or equivalent in electrical or computer engineering, 4+ years in high-speed digital board design and FPGA/RTL development, US citizenship, Secret clearance eligibility, and up to 10% travel.
SystemVerilog, Verilog, VHDL, AMD Vivado, Intel Quartus, Synopsys Synplify, Mentor Xpedition, Cadence, Altium, HyperLynx, Python, TCL, Perl, ModelSim, Questa, Git, Claude Code, Copilot, DDR4, SERDES, UART, I2C, SPI, LVDS, FPGA, RTL, SoC, ADC, DAC, CI/CD, AI
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Electrical Design Engineer II
Seattle or Phoenix
$107k-$150k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
2+ YOEBS in electrical engineering,2+ years electronics hardware development,technical leadership,analog/digital circuit design,op-amp instrumentation,signal integrity,power conversion,motor drive circuits,CAD PCB layout and DO-254 exposure preferred.
3mo
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Advanced Hardware Design Engineer
Phoenix, Arizona, United States
HybridFull Time
5+ YOEBachelor’s or Master’s in Electrical/Electronic Engineering with 5+ years (Bachelor) or 3+ years (Master) hardware experience; US citizenship or permanent resident; strong schematic, testing, and analog/digital design.
Mentor Graphics Xpedition, Mathcad, LTspice, Microsoft Excel
1mo
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FPGA Digital Engineer - 2
Chandler, Arizona, United States
$87k-$131k/yr OnsiteFull Time
2+ YOEBachelor's in EE/CE or related with 2 years experience (or Master's); ability to obtain DoD Secret clearance; FPGA design experience (VHDL/Verilog), Vivado, simulation and verification skills; familiarity with Xilinx devices and digital interfaces.
Vivado IDE, Questa/ModelSim, Vitis Unified IDE, AMD Xilinx FPGAs and SoCs, VHDL, Verilog, C, C++, OSVVM, UVM
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Staff Digital Systems Engineer
Phoenix, Arizona, United States
$185k-$202k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CE, 10+ years designing FPGA/ASIC/SoC-based digital hardware, board bring-up and lab debug, high-speed interface and timing analysis, signal integrity collaboration, strong communication and leadership.
FPGA, ASIC, DDR, PCIe, Ethernet, SerDes, LVDS, SPI, I2C, Linux
2mo
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Memory Circuit Design Engineer
Hillsboro or Santa Clara or Austin or Phoenix
$122k-$232k/yr HybridFull Time
4+ YOEMaster's in EE/CE + 4+ years' experience or PhD; experience designing/characterizing memory circuits (SRAM/ROM/Register Files), PPA optimization, custom digital design, simulation, layout, verification, and knowledge of EDA tools.
EDA tools
3d
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Analog and Mixed Signal Design Engineer
Chandler or Irvine
$110k-$176k/yr OnsiteFull Time
6+ YOEMS or PhD in Electrical Engineering and 6+ years of mixed-signal and analog design experience. Requires expertise in analog circuits, layout effects, simulation, digital modeling, and EDA tools.
SPICE, Verilog, Cadence Virtuoso, Spectre, HSPICE, PrimeSim, Synopsys PrimeTime, Xcelium, VCS, Python, Perl, SKILL
3mo
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Senior Hardware Design Engineer - Space
Tempe, Arizona, United States
$156k-$246k/yr OnsiteFull Time
15+ YOEUS citizen able to obtain Active Secret clearance; deep FPGA, DSP, embedded systems and digital hardware design experience; bachelor\u0002s in EE; proficiency with lab equipment and FPGA toolchains; travel up to 10%.
Xilinx, Microchip, RTAX, RTSX, ProASIC, Synplify, ModelSim, logic analyzer, oscilloscope, DMM, power supply
1mo
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Principal FPGA Digital Engineer - 3
Chandler, Arizona, United States
$108k-$162k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE (or MS/PhD) with relevant FPGA/SoC design experience, expertise in VHDL/Verilog and Xilinx toolflow, static timing analysis, bus interfaces, simulation/verification, and ability to obtain DoD Secret clearance.
VHDL, Verilog, AMD Xilinx FPGAs, Vivado IDE, Vitis Unified IDE, Questa/ModelSim, OSVVM, UVM, AXI4, Ethernet, PCIe, UART, SDLC, DDR3, DDR4, DDR5, logic analyzer, oscilloscope, C, C++
3mo
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Sr. Staff Engineer - Digital Assets
San Francisco or Scottsdale or Chicago or New York
$175k-$240k/yr HybridFull Time
12+ YOELead architectural design for cross-border and digital asset payments; 12+ years in distributed systems; Docker; Java/Spring; cloud; SDLC experience.
Docker, Java, Spring, Kubernetes, Maven, Gradle, React, Angular, Kafka, Pub/Sub, AppDynamics