207 engineer digital design engineering jobs at 92 companies in Texas
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Digital Design Engineer - Engineering Specialist
Houston or Houston
$129k-$194k/yr OnsiteFull Time
8+ YOEBachelor’s degree in electrical engineering or related field and 8+ years of engineering experience. Requires FPGA/ASIC, VHDL/Verilog/SystemVerilog, PCB design, hardware testing, team leadership, travel, and clearance eligibility.
VHDL, Verilog, SystemVerilog, Computer-Aided Design (CAD), FPGA, ASIC, HyperLynx, PSPICE, NASA
1mo
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Senior Digital Design Engineer
Rochester or Austin or Herndon
$105k-$231k/yr OnsiteFull Time
10+ YOEBachelor's in electrical engineering or related, 10+ years digital electronics and PCB design experience, knowledge of high-speed interfaces, lab test equipment, and engineering review processes. U.S. citizenship and ability to obtain clearance required.
Siemens PADS, VHDL, Verilog, Logic Analyzers, Signal Generators, Oscilloscopes, Protocol Analyzers, Spectrum Analyzers, Network Analyzers, USB3.x, Ethernet, PCIe, I2C, SPI
3w
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Digital Layout Design Engineer
Austin, Texas, United States
OnsiteFull Time
Design custom digital layouts for ASICs, create digital macros and libraries, and collaborate with integration, CAD, circuit, and technology engineers.
CAD
2mo
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Digital Design Engineer I
Austin, Texas, United States
$79k-$146k/yr HybridFull Time
Degree in electrical/computer engineering or related field, academic/project experience in VLSI or digital IC design, knowledge of RTL, finite state machines, timing, Verilog/SystemVerilog, strong debugging and communication skills.
Verilog, SystemVerilog, EDA tools, simulation tools, verification environments
2mo
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Digital Design Engineer I
Austin, Texas, United States
$79k-$146k/yr HybridFull Time
Bachelor's degree in EE/CE or related field, academic/project experience in VLSI or digital IC design, familiarity with RTL design and Verilog/SystemVerilog, strong problem-solving and collaboration skills.
Verilog, SystemVerilog, EDA tools, simulation tools
1mo
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Senior Digital Design Engineer
Rochester or Austin or Herndon
$105k-$231k/yr OnsiteFull Time
10+ YOEBachelor's in EE,10+ years digital electronics design experience, PCB and high-speed digital expertise, proficiency with interfaces/protocols, lab test equipment experience, strong communication skills; U.S. citizenship required.
Siemens PADS, VHDL, Verilog, USB3.x, Ethernet, PCIe, I2C, SPI, Logic Analyzer, Signal Generator, Oscilloscope, Protocol Analyzer, Spectrum Analyzer, Network Analyzer
2mo
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOE5+ years experience in digital/ASIC design, degree in EE/CE or equivalent, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), RTL implementation, and ASIC design flows.
NVLink, PCI-Express, Ethernet, UCIE, RTL
2w
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Digital IC Design Engineer - USB Products
Dallas, Texas, United States
OnsiteFull Time
2+ YOEBachelor's in Electrical/Computer Engineering, 2 years digital design experience, Verilog experience, understanding of digital logic and ASIC design flow, and strong problem-solving skills.
Verilog, System Verilog, AMS, UVM, Perl, Tcl, Python
1w
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Digital Design
Austin, Texas, United States
$119k/yr OnsiteFull Time
Master’s degree in electrical, electronics, or computer engineering; knowledge of Python, C/C++, Verilog, SystemVerilog, UVM, functional verification, computer architecture, RTL design, and digital systems.
Python, C, C++, Verilog, SystemVerilog, UVM, Synopsis Design Vision, RTL, Lint, LEC, CDC, STA, RDC
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Principal Digital Design Engineer / Chip Lead
Minneapolis or Richardson or Boise
OnsiteFull Time
10+ YOEBS, MS, or PhD in engineering; 10+ years of ASIC/digital design experience with prior tape-out; expert SystemVerilog; synthesis, timing analysis, RTL simulation, CDC, IP integration, and technical leadership experience.
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Tempus, VCS, Xcelium, Verdi, DVE, SpyGlass, JasperGold CDC, I2C, PRBS
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Principal Digital Design Engineer / Chip Lead
Minneapolis or Richardson or Boise
OnsiteFull Time
10+ YOEBS, MS, or PhD in engineering; 10+ years of ASIC/digital design experience and prior tape-out; expert SystemVerilog; synthesis, timing analysis, RTL simulation, CDC, IP integration, and technical leadership experience.
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Tempus, VCS, Xcelium, Verdi, DVE, SpyGlass, JasperGold CDC, SDC, I2C, SerDes, DDR, PRBS, DFT, ATPG
1mo
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Senior Staff Digital Design Engineer
Plano, Texas, United States
HybridFull Time
5+ YOE5+ years in digital IC design with Verilog/SystemVerilog, RTL, synthesis, STA, verification, silicon debug, UVM and experience with industry EDA tools; B.Tech/M.Tech in electronics or related field.
Verilog/SystemVerilog, UVM, I²C, I3C, SPI, UART, Python, Tcl, Perl, Shell, Xcelium, Genus, SpyGlass, OneSpin/JasperGold, Innovus, PrimeTime/Tempus, DFT, ARM, AMBA (AXI/AHB/APB), Cadence Virtuoso, STA, LEC, Lint, Formal Verification
2mo
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelors or Master's in EE/CE or equivalent experience, 5+ years relevant experience, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), delivering high-bandwidth datapath blocks, deep ASIC design flow knowledge.
NVLink Fusion, NVLink, PCI-Express, Ethernet, UCIE, RTL, SoC
2mo
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Principal Engineer, Digital Design (IO Subsystem)
Allen, Texas, United States
OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
10+ YOEBachelor's in EE (Master's preferred), 10+ years digital IC/RTL design, expert SystemVerilog, Python, UVM, UPF/STA/timing signoff, DFT experience, and strong cross-functional collaboration.
SystemVerilog, Python, UVM, UPF, STA, DFT, AI/ML
2mo
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Hardware Digital Engineer (PCB Design)
Austin, Texas, United States
HybridFull Time
5+ YOEBachelor's in Electrical, Computer, or Software Engineering; 5+ years digital hardware design; VHDL/SystemVerilog; FPGA; schematic capture; PCB layout; relocation to Austin; US work authorization without sponsorship.
VHDL, SystemVerilog, Schematic Capture, PCB Design Tools, FPGA
1w
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ASIC Digital Design Engineer (HPC IP)
Austin, Texas, United States
$114k-$170k/yr OnsiteFull Time
5+ YOEBSEE or MSEE and 5+ years in ASIC digital design and verification, with RTL expertise, EDA tools, interface protocols, analytical problem-solving, and cross-functional communication skills.
RTL, Electronic Design Automation (EDA), PCI Express (PCIe), Compute Express Link (CXL), DDR, Ethernet
2mo
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Senior Digital Hardware Design Engineer - Onsite
McKinney, Texas, United States
$87k-$165k/yr OnsiteFull Time
5+ YOEU.S. citizen with active Secret DoD clearance, STEM degree, minimum 5 years relevant experience designing and testing digital circuit card assemblies with FPGAs, processors, high-speed interfaces, schematic/CAD tools, and lab integration.
FPGA, ECAD, Siemens Xpedition, xDX Designer, xPCB Layout, HyperLynx, Xpedition Constraint Editor System (CES), Earned Value, Agile Execution
2mo
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Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
10+ YOEBS/MS in EE, 10+ years digital CMOS IC design experience, Verilog/System Verilog expertise, low-power (UPF/CPF) and clocking/CDC/RDC knowledge, AXI/AHB/APB experience, scripting (Python/Perl/Tcl), and leadership of small design teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, C, Python, Perl, Tcl, Perforce, Git, Methodics
2mo
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Sr. Staff Engineer - Digital Design Verification
Austin, Texas, United States
OnsiteFull Time
8+ YOEBSEE or MSEE with 8+ years verifying complex SoC digital designs using SystemVerilog/UVM and C/C++; proven tape-outs, SoC-level verification, and strong collaboration and debugging skills.
SystemVerilog, UVM, Verilog, C/C++, Python, Perl, Makefile
2mo
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Principal Engineer DSP PHY Digital Design
Dallas, Texas, United States
HybridFull Time
10+ YOEB.S. +10 yrs or M.S. +7 yrs in EE/CE or related; strong digital communications/DSP fundamentals; experience with high-speed wireline DSP (FFE/DFE, CDR, FEC), RTL design/verification; C++, MATLAB proficiency.
C++, MATLAB, Python
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