9 formal verification engineer jobs at 4 companies in Chula Vista, CA
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Lead Formal Verification Engineer
Austin or Orlando or San Diego
$156k-$268k/yr HybridFull Time
Undergraduate degree required; master's or PhD preferred. Requires formal verification expertise, SystemVerilog Assertions, EDA tools, processor architecture, verification infrastructure, and convergence techniques.
SystemVerilog Assertions (SVA), JasperGold, VC Formal, Murphi
1mo
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ASICS Design Verification Engineer
San Diego, California, United States
$116k-$173k/yr OnsiteFull Time
2+ YOEBachelor's in engineering or science and 2+ years ASIC design/verification experience (Master's/PhD alternatives available). Experience with SystemVerilog/UVM, testbench development, coverage, assertions, UPF, formal verification, and scripting (Perl/Python).
SystemVerilog-UVM, SystemVerilog, Verilog, VHDL, C, C++, Perl, Python, UVM, OVM, Unified Power Format (UPF), AMBA, AXI, AHB, APB
1mo
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SOC Verification and Methodology Engineer
San Diego, California, United States
$164k-$246k/yr OnsiteFull Time
6+ YOEDevelop and execute SystemVerilog/UVM verification plans for SoC designs; debug issues; collaborate with cross-functional teams. Bachelor’s (or higher) in science/engineering plus relevant ASIC verification experience required.
SystemVerilog, UVM, Perl, Python, Formal tools
5d
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ASICS Design Verification Engineer-Senior
San Diego, California, United States
$116k-$173k/yr OnsiteFull Time
2+ YOERequires a bachelor's degree and 2+ years of ASIC experience, or a master's degree and 1+ year, or a PhD. Preferred experience includes SystemVerilog, UVM, RTL, C/C++, Python or Perl, and formal verification.
SystemVerilog, UVM, UPF, Perl, Python, C, C++, Verilog, VHDL, OVM, AMBA, AXI, AHB, APB
2w
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Mixed Signal Design Verification Engineer
San Diego, California, United States
$140k-$210k/yr OnsiteFull Time
2+ YOEBachelor's, master's, or PhD in science, engineering, or related field with 2–6+ years of ASIC design verification or related experience; SystemVerilog/UVM, simulation, formal tools, and scripting knowledge required or preferred.
SystemVerilog, UVM, VCS, Xcellium, NCsim, Modelsim, Questa, VCFormal, Jaspergold, 0In, Python, Perl, SVA
2mo
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Sr. ASIC Design Verification Engineer, Amazon Leo
Sunnyvale or San Diego or Los Angeles County
$159k-$248k/yr OnsiteFull Time
7+ YOEBachelor's in CS/CE/EE, 7+ years verification experience (communications preferred), 5+ years with UVM and C/C++ and scripting, familiarity with Matlab and formal verification preferred; must meet U.S. export-control eligibility.
UVM, SystemC, DPI-C, Matlab, C/C++, FPGA
2w
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TPU Design Verification Engineering Lead
Mountain View or San Diego
$192k-$278k/yr OnsiteFull Time
10+ YOE10+ MgmtBachelor's degree or equivalent practical experience; 10 years managing functional verification for IPs and SoCs. Expertise in verification methods including formal, GLS, UPF, UVM, and C-based testing.
GLS, UPF, UVM, C
2d
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Camera DV Engineer
San Diego, California, United States
$148k-$223k/yr OnsiteFull Time
4+ YOEBachelor's degree and 4+ years of related engineering experience, or master's degree with 3+ years, or PhD with 2+ years. Requires SystemVerilog, OVM/UVM, digital design, RTL debugging, and constrained-random verification expertise.
SystemVerilog, OVM, UVM, Verilog, RTL, Simulation, Formal, Assertion, Emulation
2mo
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Processor Micro Architect RTL Design Engineer (Multiple Levels)
San Diego, California, United States
$180k-$271k/yr OnsiteFull Time
4+ YOEDegree in EE/CS/CE; minimum 4+ years experience (PhD+4, MS+5, BS+6). Expertise in RTL/Verilog/System Verilog, synthesis, static timing analysis, CDC, PLDRC, formal verification, low-power and microprocessor design.
RTL, Verilog, System Verilog, PLDRC