5d
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Formal Verification Engineer
Boxborough or Austin or Boston or Santa Clara
HybridFull Time
8+ YOE8+ years design verification experience with strong focus on formal verification, proficiency with VC Formal/JasperGold, SVA, formal methods, and scripting (TCL, Python, Perl); Bachelors/Masters in CE/EE.
VC Formal, JasperGold, SystemVerilog Assertions (SVA), TCL, Python, Perl
3mo
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Formal Verification Engineer
Austin or Beaverton or Cupertino
HybridFull Time
0+ YOEBachelor's in electrical or computer engineering; formal verification knowledge preferred; scripting skills; strong problem-solving abilities.
Formal Verification Tools, Scripting Languages
1mo
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Formal Verification Engineer
San Jose, California, United States
$150k-$350k/yr OnsiteFull Time
Deep formal verification expertise, experience with assertion-based verification and proof debugging, proficiency scripting in Python or Tcl, and hands-on use of formal EDA tools to verify RTL and production IP.
JasperGold, VC Formal, Questa Formal, SystemVerilog Assertions (SVA), Python, Tcl
1mo
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Senior Formal Verification Engineer
Santa Clara or Austin
$136k-$265k/yr OnsiteFull Time
5+ YOE5+ years experience with formal verification of RTL; degree in CS/CE/EE/Mathematics or equivalent experience; experience with Verilog/SystemVerilog, formal tools, abstraction techniques, and scripting (TCL, Perl, Python).
Verilog, SystemVerilog, TCL, Perl, Python
1mo
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Senior Formal Verification Engineer
Santa Clara or Austin
$136k-$265k/yr OnsiteFull Time
5+ YOE5+ years experience with formal verification; BS/MS/PhD in CS/CE/EE/Math or equivalent; experience with Verilog/System Verilog, formal tools, abstraction techniques; scripting with TCL/Perl/Python; strong analytical and communication skills.
Verilog, System Verilog, TCL, Perl, Python
1w
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Formal Design Verification Engineer
Raleigh or Austin or Hillsboro or Mountain View or Redmond
$120k-$235k/yr HybridFull Time
1+ YOEDegree in EE/CS or equivalent plus technical engineering experience; formal verification, protocol and IP verification experience; ability to pass Microsoft Cloud Background Check and export-control screening.
Coherent Hub Interface (CHI), Advanced Microcontroller Bus Architecture (AMBA), PCIe, CXL, Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), Python
1mo
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Formal Verification - DV
San Jose, California, United States
OnsiteFull Time
5+ YOE5+ years design verification with hands-on formal verification experience; strong SystemVerilog/SVA skills; experience with commercial formal tools; deep digital design and SoC interface knowledge; strong RTL/debug skills.
SystemVerilog, SystemVerilog Assertions, UVM, Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, Python, TCL, Perl
1mo
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DV Formal Verification
Mountain View, California, United States
$200k-$420k/yr OnsiteFull Time
8+ YOEMaster's degree + 8 years formal verification experience; expertise in SVA/PSL property authoring, proof strategies, industry formal tools, debugging proof failures, and collaborating with RTL designers.
Synopsys VC Formal, Cadence Jasper
2d
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ASIC Formal Verification Engineer, Google Cloud
Sunnyvale, California, United States
$138k-$197k/yr OnsiteFull Time
4+ YOEBachelor's or equivalent, 4+ years formal and design verification experience, SystemVerilog/Verilog, experience with formal verification tools, scripting experience, strong communication and collaboration.
SystemVerilog, Verilog, Jasper, VC Formal, Questa Formal, 360-DV
1mo
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Member of Technical Staff, Formal Verification
Santa Clara or Boston
OnsiteFull Time
10+ YOEBachelor's or Master's in EE/CE, 10+ years ASIC/SoC verification with 7+ years formal verification, expertise in SVA and formal tools, scripting (Tcl/Python/Perl/Shell), strong debugging and leadership skills.
SystemVerilog Assertions (SVA), Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, UVM, Tcl, Python, Perl, Shell
2mo
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Formal Verification Engineer
Mountain View, California, United States
$140k-$420k/yr HybridFull Time
0+ YOEHands-on hardware model checking with SVA/PSL; experience with interactive theorem provers (Lean, Coq, Isabelle/HOL); embedding languages/IR into provers; familiarity with compiler correctness proofs.
JasperGold, VC-Formal, Lean 4, Rocq, Isabelle/HOL, SVA/PSL, Coq, Agda
4d
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Sr. Formal Verification Engineer, Annapurna Labs
Austin or Cupertino
$159k-$248k/yr OnsiteFull Time
7+ YOEBachelor's in CS/EE,7+ years formal verification experience as IP/block owner, expertise in abstraction and end-to-end checking, RTL and microarchitecture comprehension, and coding/scripting skills.
C, C++, C#, Node.JS, Java, Python, PHP, Ruby
1mo
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Senior Staff Engineer, GPU Design Verification (Formal Verification)
San Jose, California, United States
$198k-$297k/yr OnsiteFull Time
8+ YOE8+ years verification experience (formal verification focus), proficiency in formal methods, System Verilog/SVA, Python/Perl/C++, EDA formal tools, strong debugging and architecture knowledge; BS/MS/PhD in CS/CE/related.
Python, Perl, C/C++, System Verilog, System Verilog Assertions (SVA), Confluence, JIRA, Universal Verification Methodology (UVM), UPF
1w
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Formal Design Verification Engineer (200043575)
United States
OnsiteFull Time
No qualifications or requirements provided in the posting.
1mo
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Senior Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBSEE+5yrs or MSEE+3yrs or PhD+1yr; expertise in Verilog/SystemVerilog, OVM/UVM, formal methods; knowledge of DDR, PCIe, AMBA; scripting in Python/Perl and UNIX/Linux; strong debugging and verification planning skills.
Verilog, SystemVerilog, VHDL, OVM/UVM, SystemVerilog assertions (SVA), DDR, PCIe, AMBA (CHI, ACE, AXI), AI/LLM, Python, Perl, UNIX/Linux
4w
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ASICS Design Verification Engineer
San Diego, California, United States
$116k-$173k/yr OnsiteFull Time
2+ YOEBachelor's in engineering or science and 2+ years ASIC design/verification experience (Master's/PhD alternatives available). Experience with SystemVerilog/UVM, testbench development, coverage, assertions, UPF, formal verification, and scripting (Perl/Python).
SystemVerilog-UVM, SystemVerilog, Verilog, VHDL, C, C++, Perl, Python, UVM, OVM, Unified Power Format (UPF), AMBA, AXI, AHB, APB
1mo
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Senior FPGA Design Verification Engineer
Sunnyvale, California, United States
$152k-$257k/yr OnsiteFull Time
Advanced knowledge of HVL/UVM and HDL (SystemVerilog, Verilog); experience with coverage-driven verification, constrained-random testing, testbench development, scripting (Perl/Python); experience with emulation/FPGA prototyping, formal methods and ML-assisted verification is a plus.
HVL, UVM, SystemVerilog, Verilog, Perl, Python, FPGA, Emulation, Formal
3w
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
2mo
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Senior Debug Verification Engineer
San Jose, California, United States
$149k-$215k/yr OnsiteFull Time
8+ YOE8+ years ASIC/design verification; SystemVerilog; UVM and formal verification; Linux/Unix scripting with Perl or Python; strong cross-site collaboration.
SystemVerilog, UVM, Formal verification, Linux, Perl, Python, Emulation, JTAG, PCIe, USB
1mo
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Design Verification Engineer IV
San Jose, California, United States
$112k-$176k/yr OnsiteFull Time
6+ YOEExpertise in SystemVerilog/UVM, AXI/PCIe/Ethernet/NOC/UCIe protocols, CPU architectures (ARM, RISC-V) and C/C++; 6–8+ years verification experience; formal verification and scripting experience; ability to architect SoC verification environments.
SystemVerilog (SV), UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, C++
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