4 formal verification engineer jobs at 3 companies in Sacramento, CA
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Design Verification Engineer
Santa Clara or Folsom or Austin
$166k-$250k/yr HybridFull Time
6+ YOEExperienced verification engineer with SystemVerilog, UVM, C/C++, Python or Perl, DDR memory verification, formal verification, and cross-functional hardware, firmware, and software collaboration experience.
SystemVerilog, UVM, C, C++, Python, Perl, DDR5, LPDDR5, LPDDR6, DFI, DIMMs, RTL, BIOS, GLS, NLP, XPROP, VIPs, BFMs
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Design Verification Engineer
Rancho Cordova, California, United States
$121k-$194k/yr HybridFull Time
3+ YOEMaster's degree with 3+ years or bachelor's degree with 5+ years in engineering or computer science; pre-silicon memory verification, UVM, SVA, formal verification, mixed-signal simulation, and scripting experience required.
UVM, SystemVerilog Assertions (SVA), Python, Perl, AI-assisted workflows
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Technical Staff Engineer - Verification
Chandler or San Jose or San Jose or Roseville or Austin
$91k-$232k/yr OnsiteFull Time
12+ YOEBS or MS in electrical/electronic engineering and 12+ years verifying complex SoC designs. Requires SystemVerilog, UVM, formal verification, methodology development, automation, scripting, and SoC architecture expertise.
SystemVerilog, UVM, Python, TCL/TK, C, C++, Siemens, Cadence, Synopsys, Git, Perforce, svn, ARM, RISC-V, PCIe, DDR4, DDR5, LPDDR4X, MIPI DSI, MIPI CSI, Ethernet MAC, USB, FPGA, SoC, RTL, GDS
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Design Verification Engineer
Santa Clara or Folsom or Austin
$153k-$229k/yr HybridFull Time
8+ YOEAdvanced SystemVerilog, UVM, C/C++, Python or Perl, and formal verification experience; bachelor's plus 8 years or master's plus 6 years in a related discipline preferred.
SystemVerilog, UVM, C, C++, Python, Perl, DFI, DDR5, LPDDR5, LPDDR6, DIMM, RTL, BIOS, GLS, NLP, XPROP, VIP, BFM