9 formal verification engineer jobs at 7 companies in Vacaville, CA
3mo
Save
Mark Applied
Hide
Formal Verification - AI/ML Engineer
Austin or San Francisco
HybridFull Time
10+ YOEBachelor's degree with 10+ years of industry experience; strong Python/ML, LLMs, RAG, and FV domain knowledge.
Python, PyTorch, LangChain, LlamaIndex, HuggingFace, Inference engines, Model serving
1w
Save
Mark Applied
Hide
Design Verification Engineer
Santa Clara or Folsom or Austin
$166k-$250k/yr HybridFull Time
6+ YOEExperienced verification engineer with SystemVerilog, UVM, C/C++, Python or Perl, DDR memory verification, formal verification, and cross-functional hardware, firmware, and software collaboration experience.
SystemVerilog, UVM, C, C++, Python, Perl, DDR5, LPDDR5, LPDDR6, DFI, DIMMs, RTL, BIOS, GLS, NLP, XPROP, VIPs, BFMs
1w
Save
Mark Applied
Hide
Design Verification Engineer
Santa Clara or Folsom or Austin
$153k-$229k/yr HybridFull Time
8+ YOEAdvanced SystemVerilog, UVM, C/C++, Python or Perl, and formal verification experience; bachelor's plus 8 years or master's plus 6 years in a related discipline preferred.
SystemVerilog, UVM, C, C++, Python, Perl, DFI, DDR5, LPDDR5, LPDDR6, DIMM, RTL, BIOS, GLS, NLP, XPROP, VIP, BFM
1mo
Save
Mark Applied
Hide
Digital Verification Engineer - Weapon Subsystems 2
Albuquerque or Livermore or United States
$122k-$238k/yr HybridFull Time, Temporary
Bachelor's in relevant discipline (or equivalent experience), ability to obtain DOE Q-level clearance, expertise in formal verification, VHDL/Verilog/SVA proficiency, strong analytical and written communication skills.
VHDL, Verilog, SystemVerilog Assertions (SVA)
2mo
Save
Mark Applied
Hide
Digital Verification Engineer - Weapon Subsystems 2
Livermore or California or New Mexico or United States
$122k-$238k/yr HybridFull Time, Temporary
Bachelor's degree or equivalent, ability to obtain DOE Q-level (Top Secret) clearance, several years applying formal verification to FPGA/ASIC, proficiency with VHDL, Verilog, and SystemVerilog Assertions (SVA), strong analytical and written communication skills.
VHDL, Verilog, SystemVerilog Assertions (SVA)
1mo
Save
Mark Applied
Hide
Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
2mo
Save
Mark Applied
Hide
Forward Deployed Engineer (FDE)
San Francisco or London or Budapest
OnsiteFull Time
Experience in high-accountability engineering cultures; familiarity with Rust, Java/Kotlin, or Go; domain expertise in formal methods/verification and specification-aware programming; experience with proof assistants and verification tools; strong communication with senior engineers/CTOs.
Rust, Java, Kotlin, Go, Verus, Dafny, Viper, TLA+, Lean, Roq, Isabelle
1mo
Save
Mark Applied
Hide
Senior Staff Security Engineer
Berkeley, California, United States
$170k-$223k/yr OnsiteFull Time
10+ YOE10+ years cyber security experience; systems programming in C/C++/Rust; applied cryptography; hardware root-of-trust, secure boot, HSM/HSE/TPM integration; formal verification and threat modeling.
C, C++, Rust, Go, HSM, HSE, TPM, Delay-Disruption Tolerant Networking (DTN), Bundle Protocol, NERC CIP, NIST IR 7628, NIST SP 800-160
3mo
Save
Mark Applied
Hide
Cogent AI Fellowship (Member of Technical Staff)
San Francisco, California, United States
$100k-$300k/yr OnsiteFull Time
PhD in Computer Science or related field; strong publication record or open-source contributions; research in formal methods, program analysis, PL, or runtime verification; strong engineering ability and production-minded prototype development; independent, self-starting mindset; able to work in ambiguity.