61 fpga design jobs at 13 companies in Seattle, WA
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Sr. FPGA Design Engineer
Seattle or United States
$215k-$300k/yr HybridFull Time
8+ YOEBachelor’s in Electrical or Computer Engineering; 8+ years hardware development; FPGA design, verification, and synthesis experience.
Verilog, VHDL, ModelSim, Vivado, Quartus
1mo
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Senior FPGA Design & Verification Engineer – Terwave
Seattle or California
$157k-$220k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOEBachelor's in EE/CE,7+ years FPGA design and verification experience,proficiency in VHDL/Verilog/SystemVerilog,FPGA toolchains,verification methodologies,timing closure and DSP/modem implementation.
VHDL, Verilog, SystemVerilog, UVM, Xilinx, AMD, Intel, Altera, C, C++
2mo
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
1mo
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Senior FPGA Engineer
Seattle, Washington, United States
$120k-$225k/yr OnsiteFull Time
3+ YOE3+ years FPGA design experience with VHDL or SystemVerilog; bachelor's in CS/CE/EE/math or 3+ years professional software experience; experience with complex digital, mixed-signal, or RF FPGA systems.
VHDL, SystemVerilog, RTL, Rust, C++, C, Python, Xilinx SoC, Ethernet, PCIe, JESD204C, AXI, AXI-Stream, TCL, Bash, Linux, Hardware In The Loop, Software In The Loop
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FPGA/ASIC Design Engineer (Silicon Engineering)
Irvine or Redmond
$125k-$145k/yr OnsiteFull Time
1+ YOEBachelor’s in EE/CE/CS/Physics; 1+ years RTL design (SystemVerilog/Verilog/VHDL); strong Python/C/C++, and PCB/lab experience.
Verilog/SystemVerilog, VHDL, Python, C/C++, Bash, HDL simulators, Spyglass, Vivado, Quartus, AXI/APB/AHB protocols
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FPGA Engineer (WA, Seattle)
Seattle, Washington, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Designing and maintaining FPGA IP cores and FPGA-based systems for hardware security; RTL/C/C++, Python, VHDL/Verilog, Vivado; surveillance clearance eligibility; travel up to 10%.
RTL, C/C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Zynq, Agilex, AXI, ACE, Avalon, cocotb, pyuvm
5d
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ASIC/FPGA Mid-Level Manager - Design & Verification
Tukwila, Washington, United States
$182k-$246k/yr OnsiteFull Time
10+ YOEBachelor's degree, 10+ years of ASIC/FPGA design or verification experience, SystemVerilog, hardware integration and testing, team leadership, project tracking, U.S. citizenship, and ability to obtain Secret clearance.
SystemVerilog, FAA DO-254, earned value
1d
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FPGA Engineer, Amazon LEO OISL
Redmond, Washington, United States
$136k-$184k/yr OnsiteFull Time
4+ YOERequires 4+ years of engineering or equivalent experience, FPGA prototyping and implementation, 3+ years with ASIC/FPGA design verification tools, SystemVerilog, UVM, Xilinx/AMD or Altera FPGAs, and RTL, simulation, timing, and validation expertise.
Python, SystemVerilog, UVM, Xilinx, AMD, Altera, SolidWorks, Ansys, AXI4, AXI Streaming, HDL, CI/CD
3w
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Senior Design Verification Engineer
Mountain View or Hillsboro or Redmond or San Diego
$120k-$235k/yr HybridFull Time
Experience creating emulation/simulation environments, verification using System Verilog/UVM, scripting (Python/Ruby/Perl), Verilog/C/C++, FPGA/emulation experience, and ability to meet export/security screening.
Zebu, Palladium, Verilog, System Verilog, UVM, C, C++, Python, Ruby, Perl, FPGAs, Makefiles
2w
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Senior Electrical Design Engineer
Seattle, Washington, United States
$140k-$170k/yr OnsiteFull Time
8+ YOEBachelor's in Electrical Engineering,8+ years experience,proficiency with Altium,PCBA troubleshooting,analog and digital design,microprocessor/FPGA experience,power management,wireless and sensor interfacing,excellent communication.
Altium, Confluence, JIRA, Bitbucket, Python
1mo
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Senior Software Engineer - Manufacturing and Factory
Santa Clara or Austin or Durham or Redmond or United States
$184k-$357k/yr RemoteFull Time
8+ YOE8+ years system architecture experience; BS/MS in Computer Engineering/Computer Science or equivalent; deep SW/HW interface design, networking protocols, Redfish/IPMI, GPU/DPU/FPGA system software experience, strong communication and leadership.
NVIDIA NVLink, NVIDIA InfiniBand, NVIDIA Grace CPUs, HGX, DGX, Redfish, IPMI, GPU, DPU, FPGA
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Senior Electrical Engineer, Radiation Effects & Avionics Reliability
Seattle, Washington, United States
$150k-$200k/yr OnsiteFull Time
4+ YOEBachelor’s in Electrical Engineering; 4+ years in radiation effects, avionics reliability, or high-reliability electronics; hands-on radiation testing; experience with FMEA/FMECA, FTA, derating; knowledge of FPGA/ASIC/power systems; able to translate test data into design decisions.
FPGAs, ASICs, Power electronics, COTS, Radiation test equipment, SPENVIS, OMERE, NOVICE
2h
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Principal Radar Engineer- MTI
Redmond or Seattle
$195k-$250k/yr OnsiteFull Time
8+ YOERequires a BS/MS in a relevant technical field and 8+ years in radar systems and signal processing, including MTI detection, tracking, waveform design, modeling, and algorithm development.
MATLAB, Python, Kalman, EKF, UKF, IMM, MHT, DPCA, STAP, STANAG 4607, STANAG 4676, OMS/UCI, C/C++, FPGA, GPU
1mo
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Research Scientist - DPU & AI Infra
Seattle, Washington, United States
OnsiteFull Time
2+ YOEB.S./M.S. (or Ph.D.) in CS/CE,2+ years industry experience (exception for Ph.D.),proficiency in C/C++ and Linux systems,experience in networking, distributed systems, or hardware co-design.
C, C++, Linux, OVS, SR-IOV, eBPF, DPDK, FPGA, ASIC, GPU, CUDA, NCCL
2mo
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Member of Technical Staff - Low Level & Kernels Capabilities
San Francisco or Toronto or Seattle
$200k-$350k/yr OnsiteFull Time
Experienced low-level systems engineer fluent in C/C++/CUDA and Python, kernel and kernel-optimization experience, hardware-aware coding, familiarity with LLMs, and ability to design robust, ungameable RL environments.
C, C++, CUDA, Python, assembly, cuBLAS, FFTW, OpenSSL, FPGA, RISC-V, SIMD, AVX, TPU, RTL, HDL, HLS, MLIR, LLVM, Mojo, Triton, gem5, Lean, Coq, SMT
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