129 fpga engineer jobs at 58 companies in Arlington, MD
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FPGA Developer
Fairfax, Virginia, United States
OnsiteFull Time
5+ YOEU.S. citizen able to obtain security clearance. 5+ years RTL FPGA design (VHDL/Verilog/SystemVerilog), FPGA implementation of image/signal processing, experience with Xilinx devices, high-speed interfaces, MATLAB/Python/C++, Vitis HLS/AI, and Linux driver development.
VHDL, Verilog, SystemVerilog, RTL, FPGA, Kintex, Virtex, Xilinx Zynq, Xilinx Versal, Xilinx Alveo, PCIe, CoaXPress, 10GbE, DDR, MATLAB, Python, C++, Vitis HLS, Vitis AI, Linux
2mo
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
1d
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Principal FPGA Engineer
Fairfax, Virginia, United States
$116k-$216k/yr OnsiteFull Time
9+ YOEBachelor’s degree in computer or electrical engineering plus 9+ years’ related experience, or master’s degree plus 7+ years. Requires FPGA, RTL, VHDL, SystemVerilog, Vivado, simulation, verification, and timing-closure expertise.
AMD (Xilinx), Zynq Ultrascale+ MPSoC, Zynq Ultrascale+ RFSoC, Versal ACAP, VHDL, Vivado IP Integrator, SystemVerilog, DDR4, Aurora, JESD204B/C, PCIe, Ethernet, Vivado HW Debugger, Chipscope, SmartDebug, Versal AI Engines, Microsemi (Microchip), Libero, Git, Modelsim/Questasim, Aldec, UVVM, UVM, OVM, MATLAB, Simulink, Linux, C/C++
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Principal FPGA Engineer
Ashburn or Boston or Nashua or Tewksbury
$144k-$192k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CE, 10+ years FPGA hardware development, strong RTL skills (SystemVerilog/Verilog/VHDL), FPGA toolflow experience, lab test/debug proficiency, mentorship/leadership experience, US citizenship required; active security clearance preferred.
ModelSim, Questa, Xilinx ISE, Vivado, Vivado IP Integrator, SystemVerilog, Verilog, VHDL, Zynq MPSoC, Versal Adaptive SoC, UltraScale+, Microchip Libero SoC, Intel Quartus, ChipScope, TCL, oscilloscopes, logic analyzers
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FPGA Engineer (VA, Reston )
Reston, Virginia, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and FPGA-based systems for hardware security; RTL/C/C++, Python, VHDL/Verilog; simulation, verification, system integration; verification tools and toolchains.
RTL, C/C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Xilinx, Versal, Agilex, AXI, ACE, Avalon, IP core, cocotb, pyuvm
4d
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Senior FPGA Engineer
Columbia, Maryland, United States
$96k-$182k/yr OnsiteFull Time
5+ YOESTEM degree and 5+ years of relevant experience. Requires FPGA/HDL design, high-level synthesis, integration and troubleshooting, timing closure, and Python or C programming; active Secret clearance and U.S. citizenship required.
MATLAB, Simulink, Altera, Lattice, Microchip, AMD, Cadence Stratus, Mathworks HDLCoder, Altera DSPBuilder, Python, C, oscilloscopes, logic analyzers, multimeters, Linux
1mo
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Principal FPGA Engineer
Clarksburg, Maryland, United States
$164k-$210k/yr HybridFull Time
6+ YOEU.S. citizen eligible for Secret clearance; BS EE/CompE +8yrs or MS +6yrs FPGA experience; Verilog/VHDL expertise; experience with ModelSim,Synplify Pro,Altera/XILINX/Lattice toolchains; DSP and hardware integration skills.
Verilog, VHDL, ModelSim, Synplify Pro, Altera, XILINX, Lattice, Logic analyzer, Oscilloscope
1w
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Senior FPGA Development Engineer
Germantown, Maryland, United States
$96k-$178k/yr OnsiteFull Time
3+ YOEBachelor's or master's degree in electrical or computer engineering, 3+ years of FPGA design and verification, Verilog/SystemVerilog, EDA tools, advanced verification, digital design, scripting, and debugging skills.
Verilog, SystemVerilog, Electronic Design Automation (EDA), Universal Verification Methodology (UVM), Python, Perl, Tcl, DDR, DMA, PCIe
3w
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Senior FPGA Design Engineer
Baltimore, Maryland, United States
$333k-$351k/yr HybridFull Time
12+ YOEActive TS/SCI clearance, BS in Electrical or Computer Engineering, 12+ years FPGA development experience, strong VHDL, Xilinx familiarity, Riviera PRO/Xilinx simulation and testbench experience.
VHDL, Xilinx, Riviera PRO, Verilog, SystemVerilog, Polarfire, Lattice Certus NX, C, Python
2mo
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Embedded FPGA Engineer
McLean, Virginia, United States
$87k-$198k/yr OnsiteFull Time
3+ YOE3+ years developing FPGA/SDR solutions; proficiency with Verilog/VHDL/SystemVerilog/HLS, Vitis/Vivado, Python, C++ Embedded, MATLAB, Linux; bachelor’s in EE/CE required; ability to obtain TS/SCI clearance.
Vitis HLS, Vitis, Vivado, Verilog, VHDL, SystemVerilog, Python, C++ Embedded, MATLAB, Jira, Confluence, tcl, Linux
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Embedded FPGA Engineer
McLean, Virginia, United States
$87k-$198k/yr OnsiteFull Time
3+ YOE3+ years developing FPGA/SDR solutions; proficiency with Verilog/VHDL/SystemVerilog/HLS, Vitis/Vivado/Xilinx toolchains, Python/C++, MATLAB, Linux, Agile tools (Jira, Confluence); ability to obtain TS/SCI clearance; bachelor’s in EE or CE required.
Python, C++, MATLAB, Jira, Confluence, Verilog, VHDL, SystemVerilog, HLS, Vitis HLS, Vitis, Vivado, Tcl, Linux, UNIX, AXI-Stream, AXI-Lite, DMA, RTL, SDR, SOSA, VPX, GPU, Logic Analyzer, Oscilloscope, Spectrum Analyzer
1mo
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FPGA Verification Engineer, Bespoke Solutions
Jessup or Arlington or Herndon
$136k-$184k/yr OnsiteFull Time
4+ YOERequires US citizenship and active TS/SCI clearance; Bachelor's in electrical/communications engineering; 3+ years design and 4+ years verification experience with SystemVerilog/UVM; FPGA/ASIC verification experience.
SystemVerilog, UVM, Xilinx Vivado, AMD Vivado, Synopsys VCS, Cadence Xcelium, SystemVerilog Assertions (SVA)
2d
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Digital Signal Processing and FPGA Engineer
Laurel, Maryland, United States
$100k-$245k/yr OnsiteFull Time
3+ YOEBachelor's degree in a relevant engineering or computer science field, 3+ years of software development, VHDL or Verilog, FPGA and simulation tools, GitLab, and eligibility for Secret clearance with U.S. citizenship.
MATLAB, HDL, VHDL, Verilog, Xilinx Vivado, ModelSim, GitLab, CI/CD, FPGA, RTL, GPUs, SoCs, Xilinx Zynq
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FPGA Verification Engineer Level 5 - Linthicum
Linthicum, Maryland, United States
$186k-$279k/yr OnsiteFull Time
12+ YOEBachelor's+12 years (or Master's+10, PhD+7) in EE/CE/CS, expertise in FPGA/ASIC verification, VUnit, hardware description languages, CI/CD and leadership experience; U.S. citizenship and ability to obtain TS/SCI required.
SystemVerilog, Verilog, VHDL, VUnit, Synopsys, Mentor Graphics, Jenkins, Python, Tcl, Makefile, Xilinx, MicroChip
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Sr. FPGA Developer (Hybrid- Aberdeen Proving Ground, Maryland)
Aberdeen Proving Ground or Middletown
$150k-$175k/yr HybridFull Time
10+ YOEBachelor's in EE/CE,10+ years FPGA design experience with Xilinx Vivado, Verilog/VHDL, RFSoC/Versal platforms, RTL-to-hardware validation, AXI interfaces, and eligibility for DoD Secret clearance.
Xilinx Vivado, Verilog, VHDL, Siemens Questa, Vivado Simulator, Xilinx Zynq UltraScale+ RFSoC, Zynq UltraScale+ MPSoC, Versal, Versal ACAP, ADRV9009, AD9081, ADRV9009-ZU11EG, AXI-Lite, AXI-Stream, JESD204B, JESD204C, JTAG, Integrated Logic Analyzer (ILA), VIO, Ethernet, PCIe, Tcl, Python
1w
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Principal Engineer - FPGA/ASIC Design
Reston or Washington, D.C. or Indianapolis or West Lafayette
$152k-$247k/yr HybridFull Time
5+ YOEBachelor's with 5+ years, master's with 3+ years, or PhD in electronics or computer engineering; U.S. citizenship required. FPGA/ASIC, RTL, VHDL/Verilog/SystemVerilog and verification experience required.
FPGA, ASIC, DO-254, VHDL, Verilog, SystemVerilog, TCL, Python, Shell, Windows, Linux, Git, SVN, Actel, Xilinx, MATLAB, Simulink, Cameo Systems Modeler, MagicDraw, SysML, ILA, JTAG, Microsoft Excel
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Principal Engineer - FPGA/ASIC Design
Reston, Virginia, United States
$152k-$247k/yr HybridFull Time
5+ YOEBachelor's degree plus 5+ years, master's plus 3+ years, or PhD in electronics or computer engineering; U.S. citizenship required. FPGA/ASIC, RTL, verification, timing closure, and development tool experience required.
FPGA, ASIC, VHDL, Verilog, SystemVerilog, MATLAB, Simulink, Cameo Systems Modeler, MagicDraw, TCL, Python, Shell, Windows, Linux, Git, SVN, JTAG, ILA, DO-254, SysML, Actel, Xilinx, oscilloscopes, logic analyzers
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Software Engineer (Ghidra/FPGA) 2026-0146
Annapolis Junction, Maryland, United States
$270k/yr OnsiteFull Time
Requires TS/SCI with polygraph, experience as a software engineer, knowledge of FPGA tools and Ghidra, and a bachelor's degree in a related STEM field (or 5 years hardware design experience in lieu).
Ghidra, FPGA
1w
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Senior Principal FPGA & Digital Signals Processing Engineer
Alexandria, Virginia, United States
HybridFull Time
10+ YOEBachelor's degree in a related field and 10+ years of FPGA development experience. Requires VHDL/SystemVerilog, DSP, AMD/Xilinx tools, high-speed interfaces, MATLAB/Python, C/C++, Linux, and an active Secret clearance.
VHDL, SystemVerilog, AMD/Xilinx, Vivado, Vitis, Vitis HLS, RFSoC, Versal, UltraScale+, Zynq, AXI, PCIe, Ethernet, DDR, Aurora, JESD204B/C, MATLAB, Python, C, C++, Linux, Git, CUDA, Simulink, MATLAB HDL Coder, Model Composer, RFNoC, GNU Radio, OpenCPI, SOSA, CMOSS
1mo
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Engineer
Fairfax, Virginia, United States
OnsiteFull Time
5+ YOE5+ years RTL FPGA design experience (VHDL/Verilog/SystemVerilog), experience implementing image/signal processing on FPGAs, Xilinx device experience, PCIe/CoaXPress/10GbE/DDR interfaces, MATLAB/Python/C++, Vitis HLS/AI, Linux driver experience, U.S. citizenship and ability to obtain clearance.
VHDL, Verilog, SystemVerilog, RTL, Xilinx Kintex, Xilinx Virtex, Xilinx Zynq, Xilinx Versal, Xilinx Alveo, PCIe, CoaXPress, 10GbE, DDR, Vitis HLS, Vitis AI, MATLAB, Python, C++, Linux
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