144 fpga engineer jobs at 55 companies in Garrison, MD
1mo
Save
Mark Applied
Hide
FPGA Developer
Fairfax, Virginia, United States
OnsiteFull Time
5+ YOEU.S. citizen able to obtain security clearance. 5+ years RTL FPGA design (VHDL/Verilog/SystemVerilog), FPGA implementation of image/signal processing, experience with Xilinx devices, high-speed interfaces, MATLAB/Python/C++, Vitis HLS/AI, and Linux driver development.
VHDL, Verilog, SystemVerilog, RTL, FPGA, Kintex, Virtex, Xilinx Zynq, Xilinx Versal, Xilinx Alveo, PCIe, CoaXPress, 10GbE, DDR, MATLAB, Python, C++, Vitis HLS, Vitis AI, Linux
1mo
Save
Mark Applied
Hide
FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
1mo
Save
Mark Applied
Hide
Principal FPGA Engineer
Ashburn or Boston or Nashua or Tewksbury
$144k-$192k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CE, 10+ years FPGA hardware development, strong RTL skills (SystemVerilog/Verilog/VHDL), FPGA toolflow experience, lab test/debug proficiency, mentorship/leadership experience, US citizenship required; active security clearance preferred.
ModelSim, Questa, Xilinx ISE, Vivado, Vivado IP Integrator, SystemVerilog, Verilog, VHDL, Zynq MPSoC, Versal Adaptive SoC, UltraScale+, Microchip Libero SoC, Intel Quartus, ChipScope, TCL, oscilloscopes, logic analyzers
3mo
Save
Mark Applied
Hide
FPGA Engineer (VA, Reston )
Reston, Virginia, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and FPGA-based systems for hardware security; RTL/C/C++, Python, VHDL/Verilog; simulation, verification, system integration; verification tools and toolchains.
RTL, C/C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Xilinx, Versal, Agilex, AXI, ACE, Avalon, IP core, cocotb, pyuvm
1mo
Save
Mark Applied
Hide
Senior FPGA Engineer
Fairfax, Virginia, United States
$76k-$141k/yr OnsiteFull Time
4+ YOEBachelor's in EE/CE (or MS) and 6+ years (4+ with MS) experience in FPGA RTL design, timing closure, simulation/verification, Vivado/VHDL/SystemVerilog experience, lab bring‑up, and high‑speed interface integration.
Xilinx, Zynq Ultrascale+ MPSoC, Zynq Ultrascale+ RFSoC, Versal ACAP, Versal AI Engines, Vivado Design Suite, Vivado IP Integrator, Vivado HW Debugger, Chipscope, SmartDebug, Libero, Git, Modelsim, Questasim, Aldec, UVVM, UVM, OVM, VHDL, SystemVerilog, MATLAB, Simulink, Linux, C, C++
1mo
Save
Mark Applied
Hide
Principal FPGA Engineer
Clarksburg, Maryland, United States
$164k-$210k/yr HybridFull Time
6+ YOEU.S. citizen eligible for Secret clearance; BS EE/CompE +8yrs or MS +6yrs FPGA experience; Verilog/VHDL expertise; experience with ModelSim,Synplify Pro,Altera/XILINX/Lattice toolchains; DSP and hardware integration skills.
Verilog, VHDL, ModelSim, Synplify Pro, Altera, XILINX, Lattice, Logic analyzer, Oscilloscope
1w
Save
Mark Applied
Hide
Senior FPGA Engineer, Cyber
Washington, District of Columbia, United States
$166k-$220k/yr OnsiteFull Time
Deep FPGA/SoC design experience on Xilinx or comparable platforms; proficiency in VHDL/Verilog/SystemVerilog; high-speed interfaces, precision timing, verification, lab debugging, and cross-functional collaboration.
Xilinx, VHDL, Verilog, SystemVerilog, Lattice OS, cocotb, GitLab CI/CD, Linux, oscilloscope, logic analyzer, spectrum analyzer
1w
Save
Mark Applied
Hide
Senior FPGA Design Engineer
Baltimore, Maryland, United States
$333k-$351k/yr HybridFull Time
12+ YOEActive TS/SCI clearance, BS in Electrical or Computer Engineering, 12+ years FPGA development experience, strong VHDL, Xilinx familiarity, Riviera PRO/Xilinx simulation and testbench experience.
VHDL, Xilinx, Riviera PRO, Verilog, SystemVerilog, Polarfire, Lattice Certus NX, C, Python
1mo
Save
Mark Applied
Hide
Embedded FPGA Engineer
McLean, Virginia, United States
$87k-$198k/yr OnsiteFull Time
3+ YOE3+ years developing FPGA/SDR solutions; proficiency with Verilog/VHDL/SystemVerilog/HLS, Vitis/Vivado, Python, C++ Embedded, MATLAB, Linux; bachelor’s in EE/CE required; ability to obtain TS/SCI clearance.
Vitis HLS, Vitis, Vivado, Verilog, VHDL, SystemVerilog, Python, C++ Embedded, MATLAB, Jira, Confluence, tcl, Linux
1mo
Save
Mark Applied
Hide
Embedded FPGA Engineer
McLean, Virginia, United States
$87k-$198k/yr OnsiteFull Time
3+ YOE3+ years developing FPGA/SDR solutions; proficiency with Verilog/VHDL/SystemVerilog/HLS, Vitis/Vivado/Xilinx toolchains, Python/C++, MATLAB, Linux, Agile tools (Jira, Confluence); ability to obtain TS/SCI clearance; bachelor’s in EE or CE required.
Python, C++, MATLAB, Jira, Confluence, Verilog, VHDL, SystemVerilog, HLS, Vitis HLS, Vitis, Vivado, Tcl, Linux, UNIX, AXI-Stream, AXI-Lite, DMA, RTL, SDR, SOSA, VPX, GPU, Logic Analyzer, Oscilloscope, Spectrum Analyzer
2w
Save
Mark Applied
Hide
FPGA Verification Engineer, Bespoke Solutions
Jessup or Arlington or Herndon
$136k-$184k/yr OnsiteFull Time
4+ YOERequires US citizenship and active TS/SCI clearance; Bachelor's in electrical/communications engineering; 3+ years design and 4+ years verification experience with SystemVerilog/UVM; FPGA/ASIC verification experience.
SystemVerilog, UVM, Xilinx Vivado, AMD Vivado, Synopsys VCS, Cadence Xcelium, SystemVerilog Assertions (SVA)
2w
Save
Mark Applied
Hide
FPGA Design Engineer Level 2
Linthicum Heights, Maryland, United States
$96k-$145k/yr OnsiteFull Time
2+ YOEBachelor's degree plus 2 years (or Master's with 0 years), ability to obtain U.S. government clearance, working knowledge of FPGA digital design and HDL (VHDL, Verilog), simulation, and testing.
VHDL, Verilog, AMD FPGA IDEs, Microchip FPGA IDEs, AXI4, LabView, MATLAB, Simulink
2w
Save
Mark Applied
Hide
FPGA Design Engineer Level 2
Linthicum, Maryland, United States
$96k-$145k/yr OnsiteFull Time
0+ YOEBachelor's with 2 years or Master's with 0 years; ability to obtain U.S. Secret/Top-Secret clearance; working knowledge of FPGAs, digital design and HDL (VHDL, Verilog); experience with timing, CDC, DSP, AXI4 and system-level validation.
VHDL, Verilog, AMD FPGA IDEs, Microchip FPGA IDEs, MATLAB, Simulink, LabView, AXI4
1mo
Save
Mark Applied
Hide
Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
2+ YOEUS citizenship with ability to obtain U.S. Secret clearance, Bachelor\u0000s degree in a relevant field, experience with ASIC/FPGA design or verification, and RTL experience with Verilog/VHDL/SystemVerilog.
Verilog, VHDL, SystemVerilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, ARM, JESD204C, PCIe, Ethernet
1w
Save
Mark Applied
Hide
Sr. FPGA Developer (Hybrid- Aberdeen Proving Ground, Maryland)
Aberdeen Proving Ground or Middletown
$150k-$175k/yr HybridFull Time
10+ YOEBachelor's in EE/CE,10+ years FPGA design experience with Xilinx Vivado, Verilog/VHDL, RFSoC/Versal platforms, RTL-to-hardware validation, AXI interfaces, and eligibility for DoD Secret clearance.
Xilinx Vivado, Verilog, VHDL, Siemens Questa, Vivado Simulator, Xilinx Zynq UltraScale+ RFSoC, Zynq UltraScale+ MPSoC, Versal, Versal ACAP, ADRV9009, AD9081, ADRV9009-ZU11EG, AXI-Lite, AXI-Stream, JESD204B, JESD204C, JTAG, Integrated Logic Analyzer (ILA), VIO, Ethernet, PCIe, Tcl, Python
1mo
Save
Mark Applied
Hide
Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
2+ YOEUS citizenship and ability to obtain U.S. Secret clearance; BS in engineering or related field; experience with ASIC/FPGA design or verification and HDL (Verilog/VHDL/System Verilog); familiarity with verification methodologies and scripting.
Verilog, VHDL, System Verilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, JESD204C, PCIe, Ethernet
1mo
Save
Mark Applied
Hide
Software Engineer (Ghidra/FPGA) 2026-0146
Annapolis Junction, Maryland, United States
$270k/yr OnsiteFull Time
Requires TS/SCI with polygraph, experience as a software engineer, knowledge of FPGA tools and Ghidra, and a bachelor's degree in a related STEM field (or 5 years hardware design experience in lieu).
Ghidra, FPGA
1mo
Save
Mark Applied
Hide
Engineer
Fairfax, Virginia, United States
OnsiteFull Time
5+ YOE5+ years RTL FPGA design experience (VHDL/Verilog/SystemVerilog), experience implementing image/signal processing on FPGAs, Xilinx device experience, PCIe/CoaXPress/10GbE/DDR interfaces, MATLAB/Python/C++, Vitis HLS/AI, Linux driver experience, U.S. citizenship and ability to obtain clearance.
VHDL, Verilog, SystemVerilog, RTL, Xilinx Kintex, Xilinx Virtex, Xilinx Zynq, Xilinx Versal, Xilinx Alveo, PCIe, CoaXPress, 10GbE, DDR, Vitis HLS, Vitis AI, MATLAB, Python, C++, Linux
1w
Save
Mark Applied
Hide
Hardware Design Engineer
Hanover, Maryland, United States
OnsiteFull Time
12+ YOETS/SCI with polygraph, 12+ years hardware design or reverse engineering experience, bachelor\u0002s in EE/CE (or 5 yrs substitute), extensive VHDL/FPGA and Xilinx experience, Linux and toolchain proficiency.
VHDL, FPGA, Xilinx, VIRTEX-II Pro, VIRTEX-4, VIRTEX-5, VIRTEX-6, Linux, Xilinx ISE, Synplify Pro, Modeltech's Modelsim, PERL, sh, bash, csh, python
6d
Save
Mark Applied
Hide
Senior Hardware Reverse Engineer
Linthicum or Herndon or Maryland
$150k-$215k/yr OnsiteFull Time
Bachelor's degree or equivalent practical experience; embedded systems, binary reverse engineering, debugging, bootloader, schematic, FPGA, C/C++, Python, and TS/SCI clearance experience required.
JTAG, UART, oscilloscopes, logic analyzers, C, C++, Python, AMD/Xilinx, Altera, Microsemi, FPGA, Altium, USB, SPI, I2C, 1-Wire, Ethernet, PCI-Express, 802.11, Bluetooth, ZigBee
Explore Jobs