39 fpga engineer jobs at 8 companies in Valley View, TX
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Sr FPGA Engineer
Richardson, Texas, United States
$150k-$163k/yr OnsiteFull Time
8+ YOEBS or MS in Electrical Engineering with 8+ years; DoD secret clearance; occasional travel; FPGA design with Xilinx; DSP, Linux experience.
Xilinx ISE, Vivado, VHDL, FPGA, DSP, PCIe, DDR3, Linux, Simulation, Synthesis
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Sr FPGA Engineer
Richardson, Texas, United States
$150k-$163k/yr OnsiteFull Time
8+ YOEBS/MS in Electrical Engineering with 8+ years experience, FPGA DSP design using Xilinx ISE/Vivado and VHDL, FPGA interfaces (PCIe, DDR3), MATLAB/Simulink, C and Linux experience, ability to obtain DoD Secret clearance.
Xilinx ISE, Vivado, VHDL, MATLAB, Simulink, PCIe, DDR3, Linux, C, oscilloscope, spectrum analyzer, signal generator, logic analyzer
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FPGA Engineer II
Plano, Texas, United States
$69k-$131k/yr OnsiteFull Time
2+ YOESTEM degree and 2+ years relevant experience, with FPGA/ASIC design or verification, vendor devices and tools, lab integration, Git, Python or C, CI/CD, and digital simulation experience.
AMD, Altera, Microchip, AMD Vivado, Altera Quartus Prime Pro, Libero, VHDL, Verilog, SystemVerilog, Git, Python, C, CI/CD, Questa, RivieraPro, ARM, Microblaze, NIOS, UVM, High Level Synthesis (HLS), GPUs, AES, RSA, ECC
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Senior FPGA Engineer
Kirkland or Addison
$180k-$210k/yr OnsiteFull Time
8+ YOEU.S. citizen with 8+ years FPGA experience (Xilinx/Vivado), strong Verilog skills, real-time 4K video and audio pipeline expertise, high-speed interface integration, simulation and lab debugging experience.
Verilog, Xilinx, Vivado, PCIe, DDR, Ethernet, HDMI, SDI, DisplayPort, MIPI CSI 2/DSI 2, GMSL, GigE, AXI streaming, Zynq, Linux, USB, logic analyzers, oscilloscopes
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FPGA Implementation Specialist – 5G Radio Unit Digital Front End & High-PHY Solutions
Plano, Texas, United States
$105k-$195k/yr OnsiteFull Time
3+ YOEBachelor's in engineering, 3+ years FPGA development experience in telecom, strong RTL skills (VHDL/Verilog/SystemVerilog), experience with Vivado/Vitis and AMD Versal, DSP and FPGA implementation (synthesis, place-and-route, timing), lab validation and strong technical communication.
VHDL, Verilog, SystemVerilog, Vivado, Vitis, AMD Versal
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Senior Electrical Engineer
Irving or Bronx or Sacramento or Dallas
$125k-$135k/yr OnsiteFull Time
10+ YOE10+ years electrical engineering; analog/digital circuit design; up to 600VAC; PCB layout; Ethernet/CAN/RS232; elevator domain knowledge.
Altium, Embedded C, FPGA, CAN, Ethernet, RS232/422
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Technical Staff Engineer - Applications
San Jose or Addison or Allentown or Hauppauge
$91k-$232k/yr HybridFull Time
12+ YOEBachelors in EE/Comp Eng/Science required (Masters preferred); 12+ years FPGA architecture/design experience; 5+ years lab equipment use; expert VHDL/Verilog and C; experience with Libero/Vivado/Quartus, Linux, Keil/IAR/Eclipse, EDA tools; strong communication.
Libero, Vivado, Quartus, Keil, IAR, Eclipse, Linux, C, VHDL, Verilog, RISC-V, EDA tools, Oscilloscopes, Signal analyzers
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Staff RF Power Management System Engineer
Richardson, Texas, United States
OnsiteFull Time
8+ YOEBachelor's degree in electrical engineering or related field and 8+ years' experience. Requires RF power systems, GaN/GaAs, system modeling, simulation, laboratory characterization, and technical leadership.
FPGA, E-Verify
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Manager Systems Design and Architecture
Richardson, Texas, United States
OnsiteFull Time
10+ YOEBachelor's in EE/CE/CS, 10+ years in systems architecture or hardware design, experience leading technical teams, deep knowledge of memory/storage technologies (HBM, DDR/LPDDR, NVMe), FPGA/RTL prototyping, and strong communication skills.
FPGA, RTL, HBM, DDR, LPDDR, NVMe, GPU, CPU, DPU, JEDEC, UCIe, SNIA, PCI-SIG
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HBM Hardware Emulation Architect - SMTS
Folsom or Richardson
$177k-$334k/yr OnsiteFull Time
15+ YOEBachelor's or master's degree in electrical or computer engineering, 15+ years of engineering experience, RTL design and debug, emulation platforms, memory subsystems, SoC architecture, and firmware interaction.
Palladium, Veloce, Zebu, RTL, FPGA
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