56 verification engineer jobs at 14 companies in Valley View, TX
2mo
Save
Mark Applied
Hide
Principal Digital Verification Engineer
Plano, Texas, United States
OnsiteFull Time
8+ YOE8+ years in verification; MS in Electrical/Computer Engineering or equivalent; BS with 10+ years; UVM and SystemVerilog experience; DDR5 verification
UVM, SystemVerilog, Verilog, DDR5
2w
Save
Mark Applied
Hide
Design Verification Engineer | Sensing
Dallas, Texas, United States
OnsiteFull Time
5+ YOEMasters in EE,5+ years experience in digital/AMS verification for mixed-signal chips, strong SystemVerilog skills, robust DV flow knowledge, experience with verification closure and debugging.
SystemVerilog, Cadence, ATPG, BIST, VBOX, IDDQ
2mo
Save
Mark Applied
Hide
Staff Design Verification Engineer, HBM Architecture
Richardson, Texas, United States
OnsiteFull Time
7+ YOEBachelor's in EE/CE, 7+ years verification engineering experience (including 5+ years in digital/analog/mixed-signal), 4+ years custom or RTL verification, strong communication and independent verification strategy skills.
Verilog, FastSpice, GenAI, RTL
2d
Save
Mark Applied
Hide
Staff Engineer, HBM Verification Architecture
Richardson, Texas, United States
OnsiteFull Time
7+ YOEBachelor’s degree in electrical or computer engineering, 7+ years of verification experience, 5+ years in digital, analog, or mixed-signal verification, and 4+ years in custom or RTL verification flows.
Verilog, FastSpice, GenAI, AI, JEDEC, HBM, DRAM, RTL, SoC, TSV
2mo
Save
Mark Applied
Hide
Mixed-Signal Verification Engineer – Analog IP
Allen, Texas, United States
OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
6+ YOEBachelor’s or Master’s degree in Electrical Engineering or related field; 6+ years in mixed-signal or digital IC verification; SystemVerilog and UVM proficiency; Verilog-A/AMS modeling; analog IP verification within digital-on-top SoCs.
SystemVerilog, UVM, Verilog-A/AMS, analog and mixed-signal simulation tools
2mo
Save
Mark Applied
Hide
Design Engineer Verification (2026 New College Graduate)
Richardson, Texas, United States
$72k-$148k/yr OnsiteFull Time
0+ YOEBachelor’s or Master’s in Electrical/Electronics/Computer Engineering with HDL/verification knowledge; GPA 3.0; Verilog/SystemVerilog; UNIX experience; English fluency; curiosity to learn; internship/leadership preferred.
Verilog, SystemVerilog, UNIX, Assembly, Test Bench, VLSI Design
1mo
Save
Mark Applied
Hide
Sr Principal Mixed Signal Verification Engineer
Richardson, Texas, United States
OnsiteFull Time
13+ YOEMaster's in EE, 13+ years AMS design/verification experience, proficiency in UVM, Spice/Spectre, VerilogAMS, strong debugging and communication skills; Python/shell and SV assertions preferred.
UVM, TLDV UVM, RNM, VerilogAMS, Spice, Spectre, Python, shell, SV-UDN, EENET, SV Assertions
2w
Save
Mark Applied
Hide
SoC Design Verification Engineer (2026 New College Graduate)
Richardson, Texas, United States
$86k-$148k/yr OnsiteFull Time
0+ YOEBachelor's in EE/CE or related, 0-2 years digital verification experience, Verilog/SystemVerilog, Python/Tcl/Perl, UNIX/EDA tools, strong analytical and communication skills.
Verilog, SystemVerilog, Python, Tcl/Tk, Perl, UNIX, EDA design tools, RISC-V, ARM, MIPS, C, C++
1mo
Save
Mark Applied
Hide
RTL Design/AMS Verification Engineer
Richardson, Texas, United States
RemoteFull Time
5+ YOE5+ years IC design experience; Verilog RTL design and verification experience; Cadence/Synopsys flows; AMS simulation, synthesis and APR; Bachelor's degree in Electrical Engineering; US work authorization (ITAR) required.
Verilog, Cadence, Synopsys, Python, Perl, Tcl, SKILL
1mo
Save
Mark Applied
Hide
System Engineer (Requirements/Verification)
Richardson, Texas, United States
$105k-$135k/yr OnsiteFull Time
3+ YOEBS degree in a technical field, 3+ years experience, ability to obtain Top Secret clearance with SSBI (polygraph), experience with system lifecycle engineering for high-performance signal processing systems.
DOORS, Rhapsody, Microsoft Project, JIRA, LINUX, Microsoft Office
2mo
Save
Mark Applied
Hide
Senior Systems Engineer
Grand Rapids or Wauwatosa or Henrietta or Plano
$114k-$167k/yr OnsiteFull Time
8+ YOE8+ years engineering experience, bachelor\u0002s in engineering/computer science, V-model systems engineering, SysML/MBSE, FMEA, ALM and modeling tool experience, ability to perform verification/validation and travel ~30%.
V-model, FMEA, Application Lifecycle Management (ALM), IBM DOORs, IBM Jazz, HP ALM, IBM Rhapsody, MagicDraw, SysML, MBSE
3w
Save
Mark Applied
Hide
Scientist, Chief Systems Engineer (41132)
Plano, Texas, United States
OnsiteFull Time
10+ YOEExpertise in air vehicle systems engineering, requirements definition, integration, verification/validation; 10–16+ years experience (degree-dependent); ability to obtain security clearances; MBSE experience preferred.
Microsoft Office, Matlab, LabView, Python, C, C++, C#
1mo
Save
Mark Applied
Hide
Senior Systems Engineer – EO/IR
McKinney or United States
$87k-$165k/yr OnsiteFull Time
5+ YOEU.S. citizen with active Secret clearance required; Bachelor’s in STEM and 5+ years systems engineering experience including ConOps, requirements, integration, verification, and testing; MATLAB/Python and DOORS/DNG familiarity preferred; travel up to 25%.
MATLAB, Python, DOORS/DNG, Rhapsody, Cameo, Scrum
1w
Save
Mark Applied
Hide
Autonomy Development Engineer
Mossville or Irving
$98k-$158k/yr OnsiteFull Time
Experience developing software for machine applications using C++ and Python; knowledge of SDLC, software testing/verification, camera/radar sensor testing; mining/construction experience preferred; bachelor's degree preferred; up to 10% travel; visa sponsorship available.
C++, Python
1w
Save
Mark Applied
Hide
Autonomy Development Engineer
Mossville or Irving
$98k-$158k/yr OnsiteFull Time
Experience developing software for machine applications; proficiency in C++ and Python; knowledge of SDLC and product testing; mining/construction experience preferred; camera and radar sensor test/verification and DevOps preferred; bachelor’s degree preferred; up to 10% travel; visa sponsorship available.
C++, Python
2w
Save
Mark Applied
Hide
Senior Staff Digital Design Engineer
Plano, Texas, United States
HybridFull Time
5+ YOE5+ years in digital IC design with Verilog/SystemVerilog, RTL, synthesis, STA, verification, silicon debug, UVM and experience with industry EDA tools; B.Tech/M.Tech in electronics or related field.
Verilog/SystemVerilog, UVM, I²C, I3C, SPI, UART, Python, Tcl, Perl, Shell, Xcelium, Genus, SpyGlass, OneSpin/JasperGold, Innovus, PrimeTime/Tempus, DFT, ARM, AMBA (AXI/AHB/APB), Cadence Virtuoso, STA, LEC, Lint, Formal Verification
1mo
Save
Mark Applied
Hide
Staff - Signal Integrity Engineer (Richardson, TX, US)
Richardson, Texas, United States
OnsiteFull Time
6+ YOEPlan digital PCB designs, perform signal integrity simulation and lab verification, troubleshoot high-speed interfaces, lead design reviews, develop schematics/BOMs, and validate systems; strong communication and cross-functional collaboration required.
1mo
Save
Mark Applied
Hide
SMA Production Quality Engineer (786802)
Lewisville, Texas, United States
OnsiteFull Time
3+ YOEAssociates degree or above, 3+ years manufacturing quality verification, SPC, Gage R&R, Poka-Yoke, RCA (8D/5 Whys), FMEA, Lean/Six Sigma knowledge, project management, SQL data analysis preferred, willingness to travel up to 10%.
SQL
Explore Jobs