180 fpga jobs at 65 companies in Texas
1mo
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Sr. FPGA Engineer
Singapore or Austin or Hsinchu or Shanghai or Shenzhen
OnsiteFull Time
8+ YOEBSEE/BSCE with 8+ years FPGA design and 6+ years SoC design experience. Experience with RTL/Verilog/System Verilog, FPGA bring-up, timing constraints, Xilinx Vivado/ISE, Intel Quartus Prime Pro, git, Python, and YAML.
Xilinx Vivado, ISE, Intel Quartus Prime Pro, Cadence, git, Python, YAML, Verilog, System Verilog, C, AMD VU19P, Stratix 10, AMD FPGA, Siemens proFPGA, ARM MPS4, I2C, I3C, MSPI, UART, USB
2mo
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Sr FPGA Engineer
Richardson, Texas, United States
$150k-$163k/yr OnsiteFull Time
8+ YOEBS or MS in Electrical Engineering with 8+ years; DoD secret clearance; occasional travel; FPGA design with Xilinx; DSP, Linux experience.
Xilinx ISE, Vivado, VHDL, FPGA, DSP, PCIe, DDR3, Linux, Simulation, Synthesis
1w
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Sr FPGA Engineer
Richardson, Texas, United States
$150k-$163k/yr OnsiteFull Time
8+ YOEBS/MS in Electrical Engineering with 8+ years experience, FPGA DSP design using Xilinx ISE/Vivado and VHDL, FPGA interfaces (PCIe, DDR3), MATLAB/Simulink, C and Linux experience, ability to obtain DoD Secret clearance.
Xilinx ISE, Vivado, VHDL, MATLAB, Simulink, PCIe, DDR3, Linux, C, oscilloscope, spectrum analyzer, signal generator, logic analyzer
3mo
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FPGA Engineer (TX, Austin)
Austin, Texas, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and systems; experience with RTL, C/C++, Python, VHDL/Verilog; FPGA toolchains; security clearance.
RTL, C/C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Zynq, Versal, Altera, Stratix, AXI, ACE, Avalon, cocotb, pyuvm
2mo
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Senior FPGA Design Engineer
McKinney, Texas, United States
$87k-$165k/yr OnsiteFull Time
5+ YOESTEM degree with 5+ years FPGA design experience; VHDL/Verilog proficiency; experience with Xilinx/Altera/Microchip FPGAs; onsite in McKinney, TX; DoD Secret security clearance.
VHDL, Verilog, Xilinx FPGAs, Altera FPGAs, Microchip FPGAs, Python, Perl, C
3w
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FPGA Design & Validation Engineer
Houston, Texas, United States
$60k-$100k/yr OnsiteFull Time
3+ YOEExpertise in VHDL, FPGA development and validation, lab hardware-in-the-loop testing, timing/post-synthesis verification, ADC/DAC interfacing, and 3+ years FPGA experience; B.E./M.Tech in relevant field.
VHDL, Verilog, Xilinx Vivado, Intel Quartus, Microchip Libero, Lattice FPGA, XPE, Oscilloscope, SignalTap, Logic Analyzer
2w
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System FPGA Engineer
Santa Clara or Austin
$152k-$228k/yr OnsiteFull Time
5+ YOEBachelor's or higher in engineering/CS and 5+ years FPGA implementation and verification experience; proficiency in Verilog/SystemVerilog, Python, cocotb, git/GitHub, vendor FPGA toolchains; strong communication skills.
Python, git, GitHub, cocotb, Verilog, SystemVerilog, AMD/Xilinx Vivado/Vitis, Intel/Altera Quartus Prime, JTAG, oscilloscope
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Senior FPGA Engineer
Addison, Texas, United States
OnsiteFull Time
8+ YOEBSEE or equivalent, 8+ years FPGA development experience with Xilinx, strong VHDL skills, experience with video/audio pipelines and high-speed interfaces (PCIe, DDR, Ethernet, HDMI), AXI, Zynq, and lab debugging.
VHDL, Xilinx, Vivado, PCIe, DDR, Ethernet, HDMI, DisplayPort, DSI-2, GMSL, GigE, USB, AXI, Zynq, Linux, Logic Analyzer, Oscilloscope
2w
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FPGA Design Engineer III
Austin, Texas, United States
OnsiteFull Time
3+ YOE3+ years Verilog RTL FPGA design experience, Bachelor's degree in EE/CE, full FPGA design flow knowledge, proficiency with major FPGA tool suites, and experience with verification and timing closure.
Verilog, VHDL, SystemVerilog, Microchip PolarFire SoC, RISC-V, PCIe, Ethernet, SERDES, UVM, Libero SoC, Xilinx Vivado, Intel Quartus, logic analyzers, oscilloscopes, Linux
2w
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FPGA Engineer Intern (Summer 2027 - Austin)
Austin or Chicago
OnsiteInternship
Student in Computer/Electrical Engineering (BS/MS/PhD) graduating Dec 2027–Jun 2028; hands-on FPGA/ASIC digital design experience; VHDL/Verilog/System Verilog experience; strong engineering instincts and teamwork skills.
FPGAs, ASICs, VHDL, Verilog, System Verilog
2w
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FPGA Engineer: Physical AI & Robotics
San Jose or Austin
HybridFull Time
Experienced FPGA/Adaptive SoC engineer with FPGA RTL and embedded software skills, familiarity with Verilog/SystemVerilog/VHDL, C/C++, Embedded Linux/Yocto, hardware debugging, and ability to work with customers on Physical AI solutions.
AMD Vivado, Vitis, Vitis HLS, Yocto, Verilog, SystemVerilog, VHDL, C, C++, PCIe, Ethernet, DisplayPort, MIPI CSI/DSI, USB, CAN, SPI, I2C, UART, GPIO, ROS 2, Git, JTAG, oscilloscope, protocol analyzer, logic analyzer
2mo
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Senior FPGA Engineer - Control Systems
Boulder or Austin or Berkeley
$140k-$175k/yr OnsiteFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
5+ YOESenior FPGA engineer with 5+ years in FPGA/digital design; BS in EE/Physics or related field; strong SystemVerilog, RTL, Xilinx Vivado, Zynq, C/C++, Python; Linux experience; willing to learn quantum concepts.
RTL, SystemVerilog, VHDL, Vivado, Xilinx Zynq, Git, Yocto, C, C++, Python, Linux, Prototyping
2w
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Lead FPGA Design Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBachelor's in EE/CE/CS,5+ years FPGA design experience, expertise in RTL, simulation/synthesis/timing, experience with AMD/Xilinx or Intel/Altera toolchains, familiarity with SPI,I2C,UART,Ethernet,PCIe,JESD and lab-based debug; leadership and cross-functional communication skills.
AMD/Xilinx, Intel/Altera, SPI, I2C, UART, Ethernet, PCIe, JESD, RTL, simulation, synthesis, timing analysis, digital oscilloscope, logic analyzer, function generator
1w
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Staff Engineer, FPGA Design (R5347)
Dallas, Texas, United States
$150k-$230k/yr OnsiteFull Time
Strong FPGA design, implementation, verification skills using VHDL/SystemVerilog; experience with timing closure, clock domain crossing, and high-performance digital communications; degree in STEM; Git proficiency.
VHDL, SystemVerilog, AMD/Xilinx development tools, Vivado, Git, TCL, AXI4, AXI-Stream, CI/CD
2mo
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ASIC & FPGA Design Engineer Sr
Grand Prairie, Texas, United States
$101k-$201k/yr HybridFull Time
3+ YOEBachelor's in EE or related (Master's preferred); 3+ years FPGA design and verification experience; proficiency in VHDL/Verilog/SystemVerilog, FPGA toolsets (Vivado/Vitis), simulation (Synopsys VCS), GitLab; U.S. citizenship and ability to obtain DoD Secret clearance.
VHDL, Verilog, SystemVerilog, UVM, SystemC, Python, GitLab, Vivado, Vitis, Vitis HLS, Synopsys VCS, Synopsys EDA tools, C/C++, MATLAB/Simulink, Synopsys Synplify, NCSim, ChipScope, tcpdump, Wireshark, UltraScale
3mo
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Senior FPGA & Emulation Performance Engineer
Austin, Texas, United States
$162k-$219k/yr HybridFull Time
5+ YOE5+ years in hardware emulation and FPGA environments, benchmarking and profiling skills, Linux and scripting (Python,Bash), scheduler integration, familiarity with Prometheus/Grafana and EDA vendor APIs.
Prometheus, Grafana, Linux, Python, Bash, Cadence, Synopsys, Siemens
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FPGA Engineer Engineer (eInfochips)
San Jose or Austin
OnsiteFull Time
9+ YOE9+ years experience; proficient in Verilog/System Verilog, EDA tools (VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus), IPXACT, UPF, PCIe/AXI/APB, ARM fabric; scripting with Python/Tcl/Perl; timing signoff and clock-crossing expertise.
Verilog, System Verilog, Python, Tcl, Perl, VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus, IPXACT, UPF
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FPGA Implementation Specialist – 5G Radio Unit Digital Front End & High-PHY Solutions
Plano, Texas, United States
$105k-$195k/yr OnsiteFull Time
3+ YOEBachelor's in engineering, 3+ years FPGA development experience in telecom, strong RTL skills (VHDL/Verilog/SystemVerilog), experience with Vivado/Vitis and AMD Versal, DSP and FPGA implementation (synthesis, place-and-route, timing), lab validation and strong technical communication.
VHDL, Verilog, SystemVerilog, Vivado, Vitis, AMD Versal
2mo
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FPGA Verification Engineer II
Austin, Texas, United States
OnsiteFull Time
2+ YOEBS/MS in CS, EE, or CE; 2+ years verification and automation experience; proficiency with VHDL/Verilog/SystemVerilog, C/C++, SystemC, UVM/UVMf, DPI-C, TLM, QEMU, VIP, MATLAB, Python, Linux; U.S. eligibility required per export regulations.
VHDL, Verilog, SystemVerilog, C/C++, SystemC, UVM, UVMf, DPI-C, TLM, Formal CDC, QEMU, VIP, MATLAB, Python, Linux, Xilinx
4w
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
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