85 front end engineer jobs at 32 companies in Salinas, CA
2w
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Senior Front-End Infrastructure Engineer
Austin or San Jose
OnsiteFull Time
10+ YOE10+ years (Bachelor) or 8+ (Master) or 6+ (PhD); expertise in front-end verification flows, regression management, Synopsys VCS/IES, Git/Perforce, xprop, debugging, and EDA vendor collaboration.
Synopsys VCS, IES, Git, Perforce, Git-P4, xprop
2d
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Emulation Front-End Infrastructure Engineer
Santa Clara, California, United States
$136k-$265k/yr OnsiteFull Time
3+ YOEBachelor's with 5+ years or master's with 3+ years in a related field; RTL compilation and synthesis expertise; Verilog/SystemVerilog, EDA tools, scripting, distributed compute, and version control experience.
Synopsys Design Compiler, ZeBu Compiler, Cadence HDL-ICE, Python, Perl, Tcl, Makefile, LSF, Slurm, Perforce, Git, Verilog, SystemVerilog
2d
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Sr Front-End Engineer - Campaign Experiences
Bellevue or New York City or San Francisco or San Jose or Seattle
$125k-$229k/yr OnsiteFull Time
7+ YOE7+ years of software development experience, JavaScript/TypeScript proficiency, software engineering fundamentals, enterprise service experience, and a computer science or engineering degree or equivalent experience.
JavaScript, TypeScript, C#, Java, NodeJS, SQL, React, Redux
2mo
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Senior ASIC Front End Infrastructure Engineer
Santa Clara or Westford or Austin or Durham
$184k-$357k/yr OnsiteFull Time
8+ YOE8+ years experience; Masters in Electrical Engineering, Computer Engineering, Computer Science or related; Python/Perl; AI tooling; Make; CI (Jenkins); strong problem solving; ASIC/CPU verification knowledge.
Python, Perl, Make, Jenkins
2mo
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Front end Engineer
San Jose, California, United States
$114k-$215k/yr OnsiteFull Time
Front-end engineer with TypeScript/JavaScript, React, CSS, and modern build tools; CI/CD, LLM integration, and AI-enabled UI experience.
Javascript, Typescript, React, Web Components, CSS, ES Modules, Vite, Webpack, Jenkins, CI/CD, Splunk, REST APIs, Node.js
1mo
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Multimedia Arch Senior Frontend Engineer
San Jose, California, United States
$213k-$450k/yr OnsiteFull Time
5+ YOEBA/BS in CS or related, 5+ years frontend experience, expert TypeScript/JavaScript, React, deep browser and multimedia knowledge, AI/ML integration experience, strong communication and problem-solving.
TypeScript, JavaScript, ES6+, React, WebAssembly, WebGPU, ONNX Runtime Web, Transformers.js, MediaPipe, WebCodecs, MSE, EME, WebGL, WebRTC, Web Audio API, WebNN, Web Workers, Golang
2mo
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Frontend Engineer, Media Infra Systems & Observability - L4
Los Gatos, California, United States
$250k-$413k/yr OnsiteFull Time
Strong frontend skills in React, TypeScript, GraphQL; experience with data-heavy UIs; ability to define requirements with engineering partners; familiar with backend reading/debugging.
React, TypeScript, GraphQL
4w
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Software Engineer, Frontend
San Jose, California, United States
$156k-$186k/yr HybridFull Time
5+ YOE5+ years software engineering experience with TypeScript or similar, BS/MS or equivalent, strong problem solving, frontend web app experience, CI/CD familiarity, and collaboration skills.
TypeScript, Flow, dash-remix, Claude Code, Copilot, React Aria, Radix UI, Grafana Faro, OpenTelemetry, Sentry, GitHub Actions, Docker, Helm, Renovate, Dependabot, RSC, SSR
1w
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Senior Frontend Engineer (Full-Stack Capable)
Santa Clara, California, United States
$180k-$240k/yr OnsiteFull Time
7+ YOE7+ years frontend experience; React and TypeScript architecture; experience with complex UIs, API backend credibility, testing, accessibility, and performance.
React, TypeScript, Conductor, Next.js, Java, Spring Boot, D3, Recharts, Tremor, VS Code, Cursor
1mo
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Sr Software Engineer, Front End
San Jose, California, United States
$179k-$268k/yr OnsiteFull Time
Expertise with TypeScript and React, frontend fundamentals (Vite, performance, security), AI-native tooling experience, data-driven instrumentation, and Mandarin proficiency; BS/MS or equivalent evidence of ability.
TypeScript, React, Vite, Playwright
3w
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Senior Director Foundry Operations and Front-End Yield Engineer
San Jose, California, United States
$232k-$290k/yr OnsiteFull Time
15+ YOEMaster's or PhD in Electrical Engineering or Material Science,15+ years semiconductor engineering experience, leadership in foundry operations, yield engineering, fab transfers, process matching, and stakeholder management.
1w
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Senior Staff RTL Design Engineer - CPU Frontend
Santa Clara, California, United States
$206k-$251k/yr OnsiteFull Time
7+ YOEBS/MS in CS/CE/EE or equivalent,7+ years RTL/CPU microarchitecture experience,Proficient in Verilog/SystemVerilog/VHDL,software engineering skills,experience with CPU front-end blocks and verification.
Verilog, SystemVerilog, VHDL, Chisel, FIRRTL, Scala, Bluespec, Git, GitHub, Jira, Confluence, UVM
1mo
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Design Lead/ Front-End Architect / Datapath Lead
San Jose, California, United States
OnsiteFull Time
10+ YOE10+ years in digital design and micro-architecture with ownership of high-throughput datapath; strong SystemVerilog/RTL, CDC discipline, UCIe/PCIe/CXL datapath knowledge, timing-aware architecture, and team leadership experience.
SystemVerilog, RTL, SVA, UCIe, PCIe, CXL, CHI, UPF, Reed-Solomon, SerDes
4d
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Senior Mobile Front-End Developer (Enterprise Supervising Technology Analyst)
San Jose, California, United States
$148k-$180k/yr HybridFull Time
4+ YOEBachelor's degree in a relevant field and four years of professional experience, including two years in application development, implementation, maintenance, or support. React experience required.
React, JavaScript, TypeScript, HTML5, CSS3, RESTful, OAuth2, JWT, CORS, Microsoft Excel
2mo
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[EM] (Full Stack & Front End) Engineering Manager Ai - BKK
Bangkok or Melbourne or Tel Aviv or Kyiv or Moscow or New Delhi or Dubai or London or Manchester or Liverpool or Łódź or Wrocław or Poznań or Rio de Janeiro or San Francisco or San Jose or Los Angeles or Chicago or New York City or Boston or Seattle or Washington or Sydney or Minsk or Toronto or Vancouver or Beijing or Shanghai or Prague or Copenhagen or Berlin or Munich or Nice or Paris
HybridFull Time
Proven people and technical leadership building large-scale web apps with React/TypeScript (or Angular/Vue); expertise with REST/GraphQL/WebSockets, performance, SSR, micro-frontends, CI/CD, testing, and mentoring engineers.
TypeScript, React, Redux, JavaScript, REST, GraphQL, WebSockets, C#, Kotlin, Scala, SSR, micro-frontends, CI/CD
2mo
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Front- End Software Engineering Technical Leader- Angular v20+
San Jose, California, United States
$184k-$264k/yr HybridFull Time
8+ YOEBachelor's in STEM with 8+ years; Angular/TypeScript/JavaScript (ES6+); large-scale web app experience; front-end architecture; NgRx Signals.
Angular, TypeScript, JavaScript (ES6+), NgRx Signals
1mo
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Senior Software Engineer (Frontend/Client Engineering)
San Jose, California, United States
$247k-$486k/yr HybridFull Time
15+ YOE15+ years industry experience in senior software engineering, expertise in modern web frameworks and media playback, strong UX/UI understanding, generative AI experience, bachelor's degree in computer science (master's preferred).
React, Redux, Solid JS, Flutter, Cordova, JavaScript, TypeScript, HTML, CSS, HLS, MPEG-DASH, MSE/EME, ExoPlayer, Shaka Player, Dash.js
3mo
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ASIC Design Engineer - Pixel IP DMA
Cupertino or Sunnyvale
OnsiteFull Time
3+ YOEBachelor's degree plus 3 years of experience with front-end ASIC RTL design; experience in multimedia IP/SoC front-end design preferred.
RTL, Synthesis, Power analysis, Linting, Formal verification, AMBA (AXI, AHB, APB)
3w
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Sr. Logic Design Engineer
Santa Clara or Phoenix or Hillsboro
$142k-$200k/yr HybridFull Time
4+ YOEBachelor's in Electrical/Computer Engineering with 4+ years (or Master's w/2+, PhD w/1+) and experience in RTL/System Verilog, front-end lint/synthesis tools, VCS/Verdi, UPF, CDC and IP environment.
System Verilog, VCS, Verdi, UPF, Lint, Synthesis
2mo
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Senior Engineer, GPU RTL Design - Pixel Pipe
San Jose, California, United States
$139k-$208k/yr OnsiteFull Time
2+ YOE2+ years RTL design experience; Verilog/SystemVerilog; GPU design concepts; front-end ASIC design flows; Bachelor or Master in CS/CE
Verilog, SystemVerilog, RTL design, frontend ASIC design, timing analysis, linting, synthesis, debug
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