2w
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Senior Technical Program Manager
Redmond or Austin or Sunnyvale or Mountain View or Washington or Portland
$120k-$235k/yr HybridFull Time
4+ YOEBachelor's degree or equivalent with 4+ years experience, 2+ years managing cross-functional projects; deep hardware development and manufacturing knowledge; executive communication and stakeholder management.
4d
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SPTS Principal Program Manager
Vancouver, Washington, United States
$147k-$231k/yr OnsiteFull Time
10+ YOEBachelor's/Master's/PhD in Engineering, Science or Business; typically 10+ years experience in engineering development/NPI or program management; PMP preferred; experience with hardware development and cross‑organizational programs; strong communication and leadership.
6d
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Technical Program Management Lead (Member of Technical Staff)
Vancouver or Chandler or California
HybridFull Time
10+ YOEBachelor's in engineering or CS, 10+ years program management in semiconductor/ASIC/hardware, strong silicon development knowledge, vendor management, schedule and risk management, experience with Jira/Confluence/Smartsheet/Microsoft Project.
Jira, Confluence, Smartsheet, Microsoft Project
4w
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Technical Program Manager (Tektronix)
Beaverton or Solon
HybridFull Time
Own OEM/ODM partner relationships, drive program discipline for outsourced hardware development, translate product roadmap to executable plans; Bachelor’s in Engineering and experience in technology/manufacturing with partner engagement expected; travel up to 25%.
1mo
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Senior Director of Software Engineering
Hillsboro, Oregon, United States
$184k-$276k/yr OnsiteFull Time
10+ YOEBachelor's degree in CS/SE (Master's preferred), 10+ years software development experience with significant leadership, expertise in C#, .NET, WPF, client-server and networking (TCP/IP, WCF), hardware integration, and CI/CD practices.
.NET, C#, WPF, WCF, TCP/IP, CI/CD
3w
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Test Engineer 1 (R&D)
Houston or Corvallis or United States
$63k-$99k/yr HybridContract
B.S. in Materials/Mechanical/Nuclear/Chemical Engineering required; experience developing and managing test programs for materials or electromechanical hardware; knowledge of refractory metals preferred; eligible under DOE 10 CFR Part 810.
5d
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Silicon Packaging Design Engineer
Phoenix or Hillsboro or Chandler
$164k-$232k/yr OnsiteFull Time
10+ YOEMaster's in EE/ME, 10+ years PCB layout with Cadence Allegro and Cadence Constraint Manager, 5+ years hardware development (schematic, SI, power delivery), PCB manufacturability and DRC expertise, strong analytical and collaboration skills.
Cadence Allegro, Cadence Constraint Manager, Siemens Xpedition, Product Lifecycle Management (PLM)