2mo
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IC Package Design Engineer
Los Angeles or San Francisco or Austin
OnsiteFull Time
Bachelor's degree; IC package physical design experience; Cadence Allegro/Mentor Xpedition; SiP/PoP knowledge; high-speed and SI/PI; DRC/DFM; automation scripting.
Cadence Allegro, Mentor Xpedition, Calibre, CAM350, HFSS, PowerSI
2mo
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Sr. IC Package Design Engineer (Silicon Engineering)
Austin or Irvine
OnsiteFull Time
5+ YOEBachelor's degree in electrical/computer engineering or physics; 5+ years IC package design experience; strong SI/PI, RF, and CAD tool proficiency.
Cadence APD+/SIP, SIWave, HFSS, ADS, Package design tools
5d
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R&D Engineer IC Design 4
Austin or San Jose
$122k-$195k/yr OnsiteFull Time
6+ YOEDesign and verify RTL/Verilog blocks for ASICs including synthesis, timing closure, formal verification, scripting, and RTL/gate-level power analysis. BS/MS in ECE and 6+ years experience.
Verilog, RTL, TCL, Perl, Synopsys Design Compiler, DC topo, Cadence RTL Compiler, Primetime, liberty (LIB), Synopsys Formality, Cadence Conformal, Spyglass, svn, git
2w
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Senior IC Packaging Engineer
Hillsboro or Redmond or Mountain View or Raleigh or Austin
$120k-$235k/yr HybridFull Time
1+ YOEAdvanced IC packaging expertise with experience in 2.5D/3D packaging, substrate/interposer design, supplier management, reliability assessment, and EDA/PCB layout tools; advanced degree or equivalent experience required.
Cadence Allegro
3d
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Senior IC Package Design Engineer - TeraWave
San Diego or Austin or California
$230k-$323k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOEBachelor's in EE or related,7+ years industry experience delivering IC packaging,expertise with HFSS/EMX/Momentum,Cadence Allegro experience preferred,RF/mmWave and power/signal integrity expertise,U.S. work authorization required.
HFSS, EMX, Momentum, Cadence Allegro
2mo
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Analog Design Engineer
Austin, Texas, United States
$317k/yr OnsiteFull Time
10+ YOE10+ years analog/mixed-signal IC design; MS or PhD in Electrical Engineering; 25 Gbps SerDes experience; Cadence tools; post-silicon bring-up; collaborative team player.
Cadence Virtuoso, Cadence Spectre, Verilog-A, EM-IR, Monte Carlo, Post-silicon test equipment
1mo
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Analog Design Engineer
Austin, Texas, United States
OnsiteFull Time
Experience in analog/mixed-signal IC design, transistor-level design and simulation, circuit verification, collaboration across cross-functional teams, and silicon bring-up/debugging.
2mo
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Senior Analog Design Engineer
Austin, Texas, United States
$125k-$231k/yr HybridFull Time
3+ YOEMS in Electrical Engineering or equivalent with 3+ years analog/mixed-signal IC design; strong CAD, UNIX, MATLAB skills; good communication and leadership potential.
UNIX, MATLAB, Cadence (CAD tools), Verilog, VerilogA, Scripting (Tcl, Perl, SKILL)
2mo
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CPU Physical Design Engineer
Austin, Texas, United States
$142k-$269k/yr OnsiteFull Time
6+ YOEBachelor’s or Master’s in Computer/Electrical Engineering with 4-6+ years experience; strong IC physical design, synthesis, and verification skills.
Synopsys, Cadence, TCL, EDA tools, Static Timing Analysis tools, Power analysis tools
1mo
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Analog Design Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years designing advanced analog/mixed-signal ICs (PLLs, ADCs/DACs, SerDes, timing circuits) with FinFET/GAA process experience; B.Sc/M.Sc in EE/CE; tape-out, layout understanding, verification, and teamwork skills.
1mo
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Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
10+ YOEBS/MS in Electrical Engineering, 10+ years digital CMOS IC design experience, expertise in Verilog/System Verilog, UPF/CPF, AXI/AHB/APB, RTL design, synthesis, timing, power analysis, simulation, scripting (Python/Perl/Tcl), and leading small teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, RISC-V, C, Python, Perl, Tcl, Perforce, Git, Methodics
2mo
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Design & Verification Engineer, Analog Power Management (7682) (Austin, TX, US)
Austin, Texas, United States
$120k-$170k/yr OnsiteFull Time
7+ YOEMSEE with 7+ years in hands-on power management design/verification; SIMPLIS knowledge; PCB design/layout in PM; IC design/packaging familiarity; strong teamwork; power delivery modeling
SIMPLIS, PCB Design, Power Delivery Modeling
3mo
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Sr. Physical Design Verification Engineer, Annapurna Labs
Cupertino or Austin
$159k-$248k/yr OnsiteFull Time
5+ YOEExperience in physical verification for advanced nodes (5+ yrs), scripting (Python/Perl), expert knowledge of Calibre/IC Validator/PVS, BS+10 or MS+7 in EE/CS or related, proven tape-out experience.
Calibre, IC Validator, PVS, Python, Perl, FC, Innovus
3mo
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Full-Chip Physical Design Verification Engineer
Austin or Fort Collins or Santa Clara
$100k-$500k/yr HybridFull Time
7+ YOE7–14 years of hands-on CPU/IP/SoC physical verification experience; strong DRC/LVS/ERC/DFM tooling skills; scripting in Python and TCL.
Calibre, ICV, Pegasus, FC, Innovus, Python, TCL
6d
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Sr. Electrical Engineer
Austin, Texas, United States
$91k-$177k/yr OnsiteFull Time
5+ YOEAdvanced analog/mixed-signal IC design experience, MOS transistor and device physics knowledge, layout and verification familiarity, simulation and modeling skills, and strong written/verbal communication.
UNIX
1mo
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Senior CPU Power Delivery Engineer
Austin, Texas, United States
$152k-$255k/yr OnsiteFull Time
5+ YOEBS/MS/PhD in electrical engineering, 5+ years power delivery/power integrity experience for digital ICs, PDN simulation tool experience, CPU power knowledge, advanced-node physical design experience.
Apache Redhawk, Voltus, SIwave, oscilloscope, VNA, PDN analyzer
3w
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Sr. Principal Technical Quality Engineer
San Jose or Austin or Cary
$154k-$286k/yr OnsiteFull Time
7+ YOEMSEE and 7+ years experience in IC design/verification or silicon quality; defect analysis and RCA experience; strong communication and problem-solving skills.
1mo
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PMTS, A&D Field Application Eng
Austin or Santa Clara or Richardson or Malta
$145k-$236k/yr OnsiteFull Time
15+ YOEBachelor's degree in electrical engineering (or equivalent), extensive semiconductor IC design/tapeout/process experience, eligible for U.S. Secret clearance, strong IC design flow and EDA tool knowledge, customer engagement and program management skills.
EDA
3w
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Senior Staff Engineer, Physical Implementation CAD Lead
Austin or San Jose
$180k-$297k/yr OnsiteFull Time
11+ YOE11+ years physical design/CAD experience (or equivalent with advanced degree); expertise in P&R flows, timing, power optimization, Cadence/Synopsys toolsets, physical verification, sub-5nm challenges; scripting with Python/Tcl/shell; strong collaboration and mentoring skills.
Cadence, Synopsys, Calibre, ICV, Python, Tcl, shell
3w
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MTS Field Application Eng - RF & Photonics
Santa Clara or Richardson or Austin
$99k-$161k/yr OnsiteFull Time
10+ YOEBachelor's in electrical engineering or equivalent, 10+ years semiconductor design/tapeout/process experience, knowledge of IC design flows and EDA tools, strong communication and program management skills.
EDA tools