189 interconnection engineer jobs at 68 companies in Campbell, CA
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Transmission & Interconnection Manager
Houston or Oakland or Golden or Reno or Salt Lake City
HybridFull Time
5+ YOEBachelor’s in Electrical Engineering; 5+ years in generation interconnection and transmission; strong stakeholder management; analytical and independent.
1mo
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Interconnection Manager, Network Strategy Americas
San Francisco or Austin or New York City or Washington
$143k-$207k/yr HybridFull Time
5+ YOE5+ years network infrastructure experience; expertise with interconnection agreements, capacity planning, cost modeling, BGP/DWDM/IP networking; strong negotiation, analytical, and communication skills; familiarity with AI tooling.
BGP, DWDM, IP networking, AI
2mo
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Director, Interconnection Execution
Durham or Asheville or Chicago or New York City or Washington or San Francisco
$200k-$240k/yr HybridFull Time
6+ YOEBachelor's degree in engineering/business/energy systems, 6+ years in grid interconnection or utility project management, experience managing GIA compliance, strong knowledge of FERC LGIP/LGIA and ISO/RTO processes, negotiation and stakeholder management skills.
1mo
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Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
$179k-$219k/yr OnsiteFull Time
Design and implement TileLink interconnect, cache controllers and RTL generators; knowledge of cache coherency, NoC/interconnects, bus protocols (AXI/AHB/APB/CHI), RTL (Verilog/SystemVerilog/VHDL), and strong software engineering skills (Scala/Chisel preferred).
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, TileLink, RISC-V, AXI, AHB, APB, CHI, Git, GitHub, Jira, Confluence
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Senior RTL Engineer, Interconnect Design
San Francisco, California, United States
$225k-$445k/yr HybridFull Time
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, RDMA, RoCE, network-on-chip, NoC, FPGA, lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test
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Custom SOC IP Verification Engineer
Santa Clara or Austin
$168k-$311k/yr OnsiteFull Time
6+ YOEB.S./M.S. in engineering or equivalent experience,6+ years ASIC verification with fabric/interconnect focus,proficient in SystemVerilog and UVM,experience with interconnect protocols and scripting (Python,Perl,TCL).
SystemVerilog, UVM, AMBA AXI, CHI, Python, Perl, TCL, Palladium, Veloce, SystemVerilog Assertions (SVA)
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Project Engineer II
New York City or Mountain View or San Diego or Los Angeles
$89k-$108k/yr HybridFull Time
2+ YOEBachelor's in engineering (civil or electrical) required, 2+ years experience, proficiency with Helioscope, AutoCAD, PVSyst, Microsoft Excel, knowledge of permitting/interconnection; Procore and Salesforce a plus.
Helioscope, AutoCAD, PVSyst, Microsoft Excel, Procore, Salesforce, Microsoft Office, Microsoft Project, CRM, Smartsheet
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Principal BESS Engineer
Scottsdale or San Francisco or San Diego or Houston or Denver or Princeton
$140k-$195k/yr HybridFull Time
8+ YOERequires 8+ years in utility-scale BESS engineering, integration, development, and commissioning; knowledge of electrical, fire, interconnection, controls, and safety standards; Excel and Python skills.
Microsoft Excel, Python, TCP/IP, Modbus/TCP, Power Plant Controller, Energy Management Systems (EMS), Battery Management Systems (BMS), SCADA, UL/IEEE, National Electrical Code, NFPA 855, NFPA 72, NFPA 68, NFPA 69, UL1973, UL9540/A
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Field Service Engineer
Santa Clara, California, United States
$90k-$148k/yr FieldFull Time
5+ YOEBachelor's in engineering, 5+ years field service or hands-on engineering experience, familiarity with interconnect systems, signal integrity, and electrical testing; strong communication and diagnostic skills; willing to travel.
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Sr. Electrical Engineer- Power Generation
Denver or San Diego or San Francisco or Texas
$140k-$165k/yr HybridFull Time
8+ YOE8+ years electrical engineering experience for data centers or power generation; expertise with gas turbines, gas engines, onsite generation, medium-voltage distribution, protection, and grid interconnection.
SCADA
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Field Applications Engineer (FAE)
Santa Clara, California, United States
$111k-$166k/yr OnsiteFull Time
2+ YOEBachelor's in engineering or equivalent,2+ years design/applications engineering experience in interconnect or electrical hardware,proficiency with Creo/SolidWorks and Microsoft Office 365,strong communication and project management skills.
Creo, SolidWorks, Microsoft Office 365, Microsoft Excel, Microsoft PowerPoint
2w
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Senior Electrical Engineer – Infrastructure Power Systems (Owner's Engineer)
Berkeley, California, United States
$180k-$198k/yr HybridFull Time
8+ YOEPE in California, 8+ years (or MS+5 or equivalent) experience in HV/MV power systems, power system study and protection expertise, utility interconnection experience, and ability to act as owner’s engineer.
SKM PTW, ETAP, EasyPower, Schneider Electric Power Monitoring Expert (PME), ION, AutoCAD, Bluebeam, SCADA
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Solutions Engineer – Optical Solutions
Santa Clara, California, United States
$168k-$280k/yr OnsiteFull Time
10+ YOE10+ years in optical communications, bachelor\u0002s in electrical engineering, deep expertise in silicon photonics, high-speed interconnects, optical test equipment, customer collaboration, and solution design.
Optical modulation analyzers, Bit Error Rate Testers (BERTs), High-bandwidth oscilloscopes, Network analyzers, Tunable lasers, Optical power meters
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Custom SOC IP Verification Engineer
Santa Clara or Austin
$168k-$311k/yr OnsiteFull Time
6+ YOE6+ years ASIC verification experience with fabric/interconnect/NoC, strong SystemVerilog and UVM skills, knowledge of interconnect protocols (AMBA AXI, CHI), scripting (Python, Perl, TCL), and degree in computer/electrical engineering or equivalent experience.
SystemVerilog, UVM, AMBA AXI, CHI, Python, Perl, TCL, Palladium, Veloce, SVA
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SoC QoS/Fabric Performance Engineer, Platform Architecture
Cupertino, California, United States
OnsiteFull Time
Experienced SoC performance engineer to develop on-chip interconnect and memory QoS features, collaborating with hardware and software teams to shape SoC architecture.
1mo
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Staff Power Systems Engineer
Burlingame, California, United States
$170k-$230k/yr OnsiteFull Time
8+ YOEBachelor's in electrical engineering, 8+ years in power systems engineering, PE or pursuing licensure, experience with utility‑scale storage/grid interconnection, knowledge of IEEE/NEC/UL/NERC, strong customer communication.
ETAP, PSCAD, PSS/E, SKM, Jama, Polarion, SCADA
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Lead Photonics System Engineer
San Jose, California, United States
$232k-$348k/yr HybridFull Time
Seasoned photonic systems engineer with experience specifying, designing, validating, and ramping integrated optical interconnect products; strong communication and cross-functional collaboration; bachelor's or master's preferred.
MSA, IEEE, OCI, QSFP, OSFP, CMIS, TDECQ, SerDes, SI/PI, FMEA, XPU
1w
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Electrical Engineer, Energy Storage Project Engineering
San Francisco, California, United States
$190k-$252k/yr OnsiteFull Time
5+ YOEBachelor's degree in engineering or equivalent experience; 5+ years desired; expertise in grid-scale energy storage, electrical design, utility interconnection, EPC execution, and applicable codes and standards.
UL 9540, UL 1973, UL 1741, IEEE, NEC, NFPA, IEC, Battery Energy Storage Systems (BESS)
3w
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Commercial Technology Engineer
United States or Los Angeles or San Jose
$140k-$160k/yr OnsiteFull Time
5+ YOEBachelor's in engineering,5+ years in fiber optics/data center or related technical-commercial roles,strong fiber optic and optical interconnect knowledge,excellent communication and presentation skills,customer-facing commercial experience.
1w
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Sr. Staff Engineer, ASIC Design
San Jose, California, United States
$180k-$223k/yr OnsiteFull Time
5+ YOERequires a BS in electrical or computer engineering, 5+ years of ASIC design experience, Verilog/SystemVerilog, ASIC verification tools, C/C++, Python, timing constraints, clock domains, and SoC interconnects.
Verilog, SystemVerilog, XCelium, VCS, Questa, C, C++, Python, Genus, Design Compiler, LEF, Cadence Virtuoso, FPGA, AMBA AXI, AMBA AHB, AMBA APB, SerDes, ATPG, BIST