238 ip jobs at 84 companies in Hollister, CA
2w
Save
Mark Applied
Hide
Senior Patent & IP Counsel
San Jose or United States
$227k-$341k/yr OnsiteFull Time
7+ YOEJ.D. and bar admission, USPTO registration, 7+ years IP experience with patent drafting/prosecution and FTO/diligence, technical bachelor’s in materials/chemistry/EE, strong drafting and M&A IP diligence experience; U.S. citizenship required.
Anaqua, CPI, PatSnap
2w
Save
Mark Applied
Hide
Director, IP
Sunnyvale or United States
HybridFull Time
10+ YOEJD and active U.S. state bar, USPTO registration, 10+ years patent prosecution experience in AI infrastructure/semiconductors, technical undergraduate or equivalent, strong communication and judgment.
1mo
Save
Mark Applied
Hide
IP Release Principal Engineer
Santa Clara or Irvine
$159k-$238k/yr OnsiteFull Time
5+ YOEBachelor's or advanced degree (or equivalent experience) with 5+ years' SoC/IP delivery experience; expertise in RTL static checks, synthesis (SDC/UPF), DFT, Verilog, Perl/Python, and SoC integration; strong communication skills.
Lint, CDC, RDC, UPF, SDC, Perl, Python, Verilog, Jira, IPMP, JTAG, BIST, PCIE/CXL
2mo
Save
Mark Applied
Hide
IP/PDK Infrastructure Engineer
San Jose, California, United States
$165k-$241k/yr OnsiteFull Time
8+ YOE8+ years in physical design enablement, CAD, ASIC flows; strong communication; IP/PDK enablement and tech file management experience.
Python, TCL, Synopsys, Cadence, Siemens, EDA tools
1w
Save
Mark Applied
Hide
Senior IP Counsel
San Jose or Addison
$154k-$228k/yr OnsiteFull Time
3+ YOEUSPTO registration, university degree in electrical engineering or related field, 3+ years patent prosecution experience (5+ preferred), JD and state bar preferred, strong patent drafting/analytical skills, travel as needed.
6d
Save
Mark Applied
Hide
PCIe IP Planner (Product Manager)
San Jose, California, United States
$149k-$216k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CS/CE,10+ years in FPGA/IP or related server/storage/acceleration domains, experience with PCIe,CXL,DMA,product planning,customer engagement,analytical and communication skills.
PCIe, Compute Express Link (CXL), Direct Memory Access (DMA), FPGA
3w
Save
Mark Applied
Hide
Mixed Signal IP Integration Engineer
Sunnyvale, California, United States
$163k-$237k/yr OnsiteFull Time
5+ YOEBachelor's or equivalent,5+ years silicon engineering,experience integrating analog/mixed-signal IPs,design integration flows,ability to coordinate cross-functional teams.
TPU, ASIC, DFT, Vertex AI
3w
Save
Mark Applied
Hide
Strategic Account IP Sales Manager
San Jose, California, United States
$154k-$208k/yr HybridFull Time
Senior sales experience in semiconductor/IP/EDA or related high-tech industry; proven enterprise account and executive relationship management; consultative selling, negotiation, and cross-functional collaboration skills.
1mo
Save
Mark Applied
Hide
RTL / Circuit IP Design Engineer
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Design and implement RTL/IP features; strong RTL/Verilog/System Verilog, UVM, UPF, SAPR, and simulation/debugging skills; scripting (Python/Perl/Ruby/Makefile/shell); Bachelors or Masters in computer/electrical engineering required.
RTL, UVM, Linux, Windows, Verilog, System Verilog, Python, Perl, Ruby, Makefile, shell, HLS, SAPR, UPF
1mo
Save
Mark Applied
Hide
SOC Infrastructure IP System HW Architect
San Diego or Santa Clara
$148k-$223k/yr OnsiteFull Time
2+ YOEDefine HW architecture for SoC infrastructure IPs; strong experience with interconnects, chiplet/Die-to-Die links, RTL design, performance modeling, HW-SW interfaces; bachelor's/master's/PhD in EE/CS or related plus relevant systems engineering experience.
ARM, X86, RISC-V, RTL, PCIe, CXL, USB, UFS, MIPI, UCIe
2d
Save
Mark Applied
Hide
Senior Legal Counsel - IP Litigation
Cupertino, California, United States
OnsiteFull Time
Patent litigator to manage patent cases, assess risks, identify resolutions, and provide strategic legal support; strong judgment and communication skills.
2d
Save
Mark Applied
Hide
Custom SOC IP Verification Engineer
Santa Clara or Austin
$136k-$265k/yr OnsiteFull Time
5+ YOEB.S./M.S. in CE/EE or equivalent,5+ years ASIC verification experience with cache coherency and memory subsystems,SystemVerilog/UVM expertise,AMBA protocols (AXI/ACE/CHI),scripting (Python,Perl,TCL),C/C++ proficiency.
System Verilog, UVM, C++, C, Python, Perl, TCL, SVA, Palladium, Veloce
4w
Save
Mark Applied
Hide
Custom SOC IP Verification Engineer
Santa Clara or Austin
$168k-$311k/yr OnsiteFull Time
6+ YOE6+ years ASIC verification experience with fabric/interconnect/NoC, strong SystemVerilog and UVM skills, knowledge of interconnect protocols (AMBA AXI, CHI), scripting (Python, Perl, TCL), and degree in computer/electrical engineering or equivalent experience.
SystemVerilog, UVM, AMBA AXI, CHI, Python, Perl, TCL, Palladium, Veloce, SVA
19h
Save
Mark Applied
Hide
Counsel, IP Compliance
San Jose or Irvine or Colorado or New York
$171k-$227k/yr HybridFull Time
2+ YOEJ.D. and membership in one state bar required; 2–3+ years as an attorney in patent or trade secret litigation or transactions, with knowledge of IP law and AI-related technical concepts.
1d
Save
Mark Applied
Hide
Counsel/Senior Counsel, IP
Sunnyvale, California, United States
$203k-$292k/yr OnsiteFull Time
6+ YOE6+ years IP practice experience, JD, California bar membership or RHIC eligibility, USPTO admission, patent prosecution and portfolio management experience, technical degree or med device/engineering background.
3w
Save
Mark Applied
Hide
Infection Prevention Nurse IP
Capitola, California, United States
$90k-$120k/yr OnsiteFull Time
California RN or LVN in good standing; knowledge of infection control, regulations, and antibiotic stewardship; APIC infection control certification preferred; Microsoft Office/Excel and PCC skills; strong communication and decision-making.
Microsoft Office, Microsoft Excel, PCC
1mo
Save
Mark Applied
Hide
IP Design Verification Engineer
Phoenix or Chandler or Hillsboro or Folsom or Santa Clara
$142k-$200k/yr OnsiteFull Time
3+ YOEDegree in EE/CE (or related) with relevant years of experience; 3+ years in SystemVerilog/Verilog and UVM/OVM; experience with Synopsys VCS, Cadence Xcelium/JasperGold, or Mentor Questa; analog behavioral modeling and PCIe/UCIe experience.
System Verilog, Verilog, UVM, OVM, Synopsys VCS, Cadence Xcelium, JasperGold, Mentor Questa, PCIe, UCIe
3w
Save
Mark Applied
Hide
ASIC Design Engineer (Video Silicon IP) - Multimedia Lab
San Jose, California, United States
OnsiteFull Time
2+ YOEM.S./Ph.D. in EE/CE, 2+ years ASIC front-end RTL ownership, proficiency in SystemVerilog/Verilog or HLS, familiarity with UVM/DPI/C++, Python scripting, and VLSI design concepts.
SystemVerilog, Verilog, High level Synthesis (HLS), UVM, DPI, C++, Python, AXI, APB, EDA, GitHub Copilot, Claude, ChatGPT, FPGA
1w
Save
Mark Applied
Hide
Avigilon Systems Administrator
Santa Clara, California, United States
$120k-$130k/yr OnsiteFull Time
3+ YOEBachelor's degree or equivalent experience,3+ years supporting enterprise physical security systems,experience with Avigilon ACC and ACM,IP networking,TCP/IP,VLANs,Windows Server,SQL,excellent communication and troubleshooting.
Avigilon Unity/ACC, Avigilon Access Control Manager (ACM), Genetec, LenelS2, Software House CCURE, Gallagher, IP Networking, Windows Server, SQL Databases, Video Analytics
1d
Save
Mark Applied
Hide
Software Engineer Graduate (Global SRE) - 2027 Start
San Jose, California, United States
$128k-$256k/yr OnsiteFull Time
Bachelor's or Master's in CS or related, strong Unix/Linux and IP networking knowledge, proficiency in Python/Go/C/C++/Java, SRE and distributed systems skills, ability to start by year-end.
Unix/Linux, IP networking, Python, Go, C, C++, Java