63 ir engineer jobs at 36 companies in Live Oak, CA
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Senior EM/IR Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
8+ YOE8+ years EM/IR analysis for complex ASICs/SoCs; power integrity; PDN design and sign-off; Verilog/SystemVerilog/UVM; scripting (Python/Tcl); experience with Cadence Voltus and Synopsys RedHawk.
Cadence Voltus, Synopsys RedHawk, Verilog, SystemVerilog, UVM, VHDL, Tcl, Python
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EMIR Engineer, Annapurna Labs - Cloud Scale Machine Learning
Austin or Cupertino
$136k-$213k/yr OnsiteFull Time
Experienced EM/IR engineer for SoC EMIR sign-off, power-grid design and analysis, EMIR flow setup, cross-domain IR analysis (die/package/board), EDA tool collaboration, and post-silicon correlation.
SystemVerilog, Make, FusionCompiler, Innovus, PrimePower, PrimeTime, ARM
2mo
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Staff Analog Layout Engineer
San Jose or Hsinchu
OnsiteFull Time
3+ YOESenior/Staff level IC layout engineer with 3-8+ years in deep-submicron analog/RF layouts; strong EDA/tool experience and EM/IR knowledge.
Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre, Siemens ICV
3mo
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Application Engineer IV
Santa Clara, California, United States
$147k-$203k/yr OnsiteFull Time
5+ YOEMS or higher in engineering or science, 5+ years relevant metrology experience, expertise in optical/X-ray/SIMS/AFM techniques, data analysis skills, ability to lead complex projects and support global teams.
Scatterometry, UV-visible, IR, XRF, XPS, HR-XRD, SIMS, TXRF-VPD, VPD-ICPMS, Nano-indentation, AFM, Photoacoustic
1mo
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ASIC Design Engineer
Santa Clara, California, United States
$116k-$190k/yr OnsiteFull Time
3+ YOEMS in Electrical or Computer Engineering (or equivalent), 3+ years experience, strong background in advanced submicron process issues, standard cell and custom ROM design, SPICE and DRC/LVS experience, EM/IR and variation simulations, and scripting (Perl, Tcl, Make).
SPICE, EM/IR, DRC/LVS, Perl, Tcl, Make, RTL
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Principal Design Engineer
San Jose or Cary
$137k-$254k/yr OnsiteFull Time
1+ YOEBS/MS/PhD in Electrical Engineering with 7/5/1+ years respectively; experience with Cadence Innovus/Tempus/QRC/Voltus/Pegasus and Palladium/Protium; Linux and Shell/Perl/TCL scripting; RTL synthesis, floorplanning, timing closure, IR drop, and industry interfaces (PCIe, DDR, LPDDR, SRAM, UCIe).
Innovus, Tempus, QRC, Voltus, Pegasus, Palladium, Protium, Linux, Shell, Perl, TCL
2w
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PD Engineer
Santa Clara, California, United States
$107k-$161k/yr OnsiteFull Time
2+ YOE2+ years physical design experience with floorplanning, place-and-route, timing closure, ECOs, IR drop and physical/formal verification; scripting in Python, PERL, TCL; Linux/Unix shell; Bachelor's degree required.
Cadence Innovus, Synopsys Fusion Compiler, Synopsys PTSI, Python, PERL, TCL, Linux/Unix shell
5d
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Staff GenAI Engineer - Early PDN Modeling
San Jose, California, United States
$170k-$290k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE/CS,5+ years in power integrity/PDN/circuit/physical/package/EDA workflows,production-quality Python coding,ML/AI applied to engineering workflows,understanding of PDN and IR drop analysis.
Python
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Physical IC Design Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOE12+ years experience in full physical design cycle (RTL to tape-out). Bachelor’s in Electrical/Electronics Engineering, Tcl/Perl scripting, proficiency with EDA tools, timing closure, EM/IR analysis, and strong communication skills.
Tcl, Perl, EDA Tools
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Senior ASIC Power Delivery Engineer
Sunnyvale, California, United States
$163k-$237k/yr OnsiteFull Time
8+ YOEBachelor's degree or equivalent; 8+ years in physical design with power delivery and advanced process nodes; experience with power grid integrity (EM/IR), place-and-route, and design-rule-check flows; EM/IR analysis and verification skills.
Unified Power Format (UPF)
5d
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Power Integrity Engineer
San Jose, California, United States
OnsiteFull Time
5+ YOEB.S./M.S. in EE,5+ years PI experience on high-current/high-performance designs, proficiency with PI EDA tools, DC IR-drop and AC impedance analysis, VRM and PCB stack-up knowledge.
Cadence Allegro, Sigrity PowerDC, PowerSI, OptimizePI, Ansys SIwave, Python, MATLAB
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Senior DFX Power Methodology Engineer
Santa Clara, California, United States
$196k-$368k/yr OnsiteFull Time
6+ YOEEngineering degree or equivalent experience with 6+–12+ years in DFT/power; strong knowledge of DFT, VLSI power/timing/voltage noise; experience with power/thermal/IR drop analysis, post-silicon debug, AI/ML for EDA, and statistical data analysis.
Power Analysis, Thermal Analysis, IR Drop tools, Applied ML, Gen AI, statistical tools, RTL, STA, place-n-route, ATE, SLT
1mo
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Physical Design Engineer
Sunnyvale, California, United States
$230k-$280k/yr OnsiteFull Time
10+ YOE10+ years physical design experience; expertise in full-chip physical verification, DRC/LVS resolution with ICV or Calibre, IR/EM analysis, 3D/2.5D packaging and die stacking; scripting with Tcl and Python; familiarity with Synopsys tools.
Synopsys, ICV, Calibre, Tcl, Python
2mo
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Senior Staff Applied AI Engineer - Context Retrieval
Mountain View or San Francisco
$229k-$343k/yr HybridFull Time
10+ YOE10+ years software engineering; deep IR and retrieval systems experience; expertise in LLM-era retrieval and agentic systems; experience building 0→1 retrieval stacks and multi-source data retrieval.
BM25, Lucene, Elasticsearch, OpenSearch, FAISS, ScaNN, HNSW, embeddings, nDCG, MRR, Recall@K, RAG, Python, Java, SQL
1mo
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Senior Software Engineer - Static Analysis
San Jose, California, United States
RemoteFull Time
7+ YOE7+ years software engineering (4+ in static/program analysis or compiler infrastructure); deep knowledge of control/data-flow, call graph construction, inter-procedural and taint/reachability analysis; strong Java/Go/C++ skills; IR/bytecode/AST experience; technical ownership.
Java, Go, C++, LLVM, MLIR, SSA, IR, bytecode, ASTs, CI/CD
4w
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Physical Design Engineer
San Jose, California, United States
$150k-$250k/yr OnsiteFull Time
7+ YOE7+ years physical design experience (synthesis, PnR, STA, timing convergence, physical verification); Bachelor's in EE/CE/CS or equivalent experience; proficiency with Innovus, Tempus, Quantus, TCL; experience with EM/IR, PDN, LEC and sub-7nm/SoC design.
Innovus, Tempus, Quantus, TCL, Cadence, Synopsys
1mo
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Power Integrity Engineer-Silicon
San Jose, California, United States
OnsiteFull Time
7+ YOE10+ years PI experience with bachelor’s (or 7+ with advanced degree); deep power integrity expertise for 2.5D/3D packaging, PDN design, transient/EM/IR analysis, simulation tool proficiency, and cross-functional leadership.
Ansys SIwave, HFSS, Cadence Sigrity, Apache RedHawk, Voltus, Keysight ADS
1w
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Sr. Staff Physical Design Engineer
Toronto or Mountain View
$191k-$219k/yr HybridFull Time
12+ YOEBachelor's in EE/CE,12+ years physical design experience with large ASIC tape-outs,timing/LVS/DRC closure,3nm experience,proficiency in TCL and Python,EM/IR and Cadence tool experience preferred.
TCL, Python, Shell, Cadence
1mo
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Laser Safety Design Engineer - Camera Hardware
Cupertino, California, United States
OnsiteFull Time
Design and develop camera and sensing hardware including visible and IR illumination and sensors; collaborate across teams to research, test, and qualify imaging and optical sensing technologies.
1mo
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Senior Compiler Engineer, GPU Code Object Rewriting & Tooling
San Jose, California, United States
$179k-$306k/yr HybridFull Time
Expertise in GPU microarchitecture and performance modeling, strong C++ systems programming, compiler/IR experience, simulation and profiler validation, technical leadership, and preferred advanced degree in CS/CE/EE or equivalent experience.
C++, AMDGPU, GCN, RDNA, CDNA, ROCm, HIP, HSA, AMDGPU LLVM backend, ROCprof, ROCm Compute Profiler, Nsight Compute, LLVM, MLIR, GCC, LLVM MC, ELF, DWARF
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