42 noc engineer jobs at 27 companies in California
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NOC Engineer / NOC Lead
California, United States
RemoteFull Time
3+ YOE3+ years in NOC/SOC/IT operations, strong Linux and networking fundamentals, experience with monitoring tools (Datadog, Prometheus, Grafana, PagerDuty), scripting (Python/Bash) preferred, strong written and verbal communication, ability to work rotating shifts.
Datadog, Prometheus, Grafana, PagerDuty, Linux, Python, Bash
5d
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Lead Data Center NOC Engineer
United States or California or Seattle or San Francisco or New York City
$126k-$157k/yr RemoteFull Time
7+ YOERequires 7+ years in NOC, data center, or infrastructure operations; incident or shift leadership; DCIM/BMS expertise; advanced L2/L3 networking; power and cooling knowledge; and on-call availability.
PLC, BMS, DCIM, Distech, Schneider, RadixIOT, UPS, PDUs, CRAC/CRAH, VLAN, VPN, Grafana, Zenduty, ServiceNow, Jira, SolarWinds, VSAT, LTE/5G, Starlink, Linux, Windows, Python, Bash, PowerShell, Microsoft, Dell, Palantir, NVIDIA, SpaceX, Skydio
5d
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NoC Interconnect Design Engineer and Architect
San Diego, California, United States
$99k-$148k/yr OnsiteFull Time
0.5+ YOEBachelor's degree in science, engineering, or related field required. Master's preferred; 6+ months of experience with architecture/design tools, scripting/programming languages, and design verification methods.
RTL to GDS Flow, Virtuoso
1mo
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Senior RTL Designer - Interconnect/NoC Design
San Jose or United States
HybridFull Time
8+ YOEBS/MS in EE/CE with 8+ years digital IC design and 4+ years owning on-chip interconnect/NoC; deep SystemVerilog, AXI/CHI, CDC, NoC, top-level integration and register-map experience required.
AXI4, AXI4-Lite, AXI-Stream, CHI, AMBA CHI, ACE, SystemVerilog, SystemRDL, IP-XACT
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Principal NoC IP Micro-Architect
San Jose, California, United States
$210k-$299k/yr OnsiteFull Time
15+ YOE15+ years in NoC IP and RTL design with SystemVerilog, strong RTL validation and SoC interconnect architecture experience; proficiency in C/C++/Perl/Python/TCL/Unix Shell; bachelor’s or master’s in EE/CE.
System Verilog, VCS, Synopsys, C, C++, Perl, Python, TCL, Unix Shell
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NoC Architect (Network on Chip)
North America or San Francisco or Austin or Boston
HybridFull Time
Hands-on experience designing, integrating, and verifying NoCs; experience making and justifying NoC IP build-versus-buy decisions; NoC and IP integration verification experience.
2mo
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Senior RTL Engineer, Interconnect Design
San Francisco, California, United States
$225k-$445k/yr HybridFull Time
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, RDMA, RoCE, network-on-chip, NoC, FPGA, lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test
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Design Verification Engineer
San Jose, California, United States
$96k-$176k/yr OnsiteFull Time
5+ YOEExpertise in SV/UVM, AXI/NOC/Ethernet/PCIe/UCIe, ARM/RISC-V with C, regression and coverage closure; typically requires 5+ years' related experience and a 4-year degree (or equivalent).
SV, UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, NVMe, NAND, DDR
3w
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AV Engineer
San Francisco, California, United States
$100k-$120k/yr OnsiteFull Time
5+ YOERequires 5+ years of AV engineering or integration experience, Crestron programming, room automation, site build-outs, vendor management, networking fundamentals, and ability to pass a background check.
Crestron, Crestron NVX, Crestron DM, Extron, Q-SYS, Zoom Rooms, Microsoft Teams Rooms, Google Meet, QSC Q-SYS, Biamp, IP addressing, VLANs, QoS, multicast, NOC
1w
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Senior Design Engineer
Mountain View or Redmond
$120k-$235k/yr HybridFull Time
5+ YOERequires a doctorate plus 1+ year, master's plus 4+ years, bachelor's plus 5+ years, or equivalent experience in electrical, computer, or related engineering. Preferred expertise includes digital design, RTL, NoC, ASIC/SoC, synthesis, and post-silicon debug.
Intellectual Property (IP), Register Transfer Level (RTL), System on Chip (SOC), Verilog, SystemVerilog, Clock Domain Crossing (CDC), NoCs, ASIC, CPU
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Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
OnsiteFull Time
Staff-level hardware engineer with experience designing interconnects, cache/coherency, RTL generators using Chisel/Scala; proficiency in Verilog/System Verilog/VHDL and hardware-software engineering practices; BS/MS in EE/CE/CS or equivalent.
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, TileLink, RISC-V, NoC, AXI, AHB, APB, CHI, Bluespec, Git, GitHub, Jira, Confluence
2w
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Senior FPGA Engineer, Networking & Security
San Jose, California, United States
$184k-$208k/yr HybridFull Time
5+ YOEBachelor's or master's degree in a relevant engineering or computer science field, 5+ years of FPGA experience, networking and cryptography expertise, HDL/RTL skills, and ability to obtain U.S. security clearance.
FPGA, SystemVerilog, Verilog, VHDL, Ethernet, SpaceWire, AES, AES-GCM, ECC, IPSec, VPN, Reed-Solomon, NoC
1mo
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Custom SOC IP Verification Engineer
Santa Clara or Austin
$168k-$311k/yr OnsiteFull Time
6+ YOE6+ years ASIC verification experience with fabric/interconnect/NoC, strong SystemVerilog and UVM skills, knowledge of interconnect protocols (AMBA AXI, CHI), scripting (Python, Perl, TCL), and degree in computer/electrical engineering or equivalent experience.
SystemVerilog, UVM, AMBA AXI, CHI, Python, Perl, TCL, Palladium, Veloce, SVA
1mo
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SoC Logic Design Engineer
Austin or Santa Clara or Hillsboro
$142k-$200k/yr HybridFull Time
3+ YOEExperience in RTL/Verilog logic design, SoC integration, low-power and timing optimization, Clock Domain Crossing and NoC architectures, AMBA protocols; bachelor's or master's in EE/CE with relevant years of experience.
RTL, Verilog, AMBA, CHI, AXI, AHB, APB, Network-on-Chip (NoC), Clock Domain Crossing
1w
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Senior RTL Engineer, IO Die and Interconnect IP
San Jose, California, United States
$138k-$206k/yr OnsiteFull Time
5+ YOEBachelor’s with 5+ years, Master’s with 3+ years, or PhD with 0+ years; 5+ years RTL development using Verilog/SystemVerilog, interconnect IP integration, SoC methodology, scripting, and high-speed IO expertise.
Verilog, SystemVerilog, UCIe, PCIe, CXL, NoC, PIPE, PHY, SerDes, SoC, IP-XACT, AXI, ACE, CHI, APB, Tcl, Python, Perl, Artificial Intelligence (AI)
1mo
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Principal SoC Architect
Walnut Creek, California, United States
$168k-$300k/yr OnsiteFull Time
12+ YOEBachelor's degree in electrical or computer engineering; 12+ years in ARM-based SoC architecture and silicon development; experience with memory, IO virtualization, Ethernet, PCIe, memory subsystems, and NoC.
ARM, Ethernet, PCIe, NoC, RTL, Tcl, Perl, Python
2w
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SRE L1 Support/Cloud Platform Ops Engineer
San Jose or Austin
RemoteFull Time
2+ YOERequires 2+ years in NOC, data center operations, or IT support; basic Linux administration; monitoring and ticketing systems experience; physical data center skills; and availability for rotating 8AM–8PM PST shifts.
Linux, Prometheus, Grafana, Nagios, ServiceNow, Jira Service Management, DCGM
1mo
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Manager of Field Applications Engineering, USA
Santa Clara or Austin
OnsiteFull Time
10+ YOE5+ MgmtBachelor's in EE/CE/STEM required; 10+ years in semiconductor/silicon IP/networking and 5+ years managing customer-facing engineering teams; deep NoC/AMBA/PCIe/CXL knowledge and EDA tool familiarity.
Synopsys, Cadence, Siemens
2w
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Member of Technical Staff — On-Chip Interconnect & High-Speed Fabric Design
Palo Alto or Bangalore
OnsiteFull Time
5+ YOEBachelor's, master's, or PhD in electrical or computer engineering; 5+ years RTL design; advanced-node tapeout; AMBA, NoC, HSIO, SystemVerilog, Python, synthesis, timing, CDC, and PPA expertise.
AMBA, AXI4, AXI5, ACE, ACE-Lite, CHI, AHB, APB, AXI-Stream, PCIe, CXL.io, CXL.mem, CXL.cache, UCIe, SystemVerilog, Python, Xilinx, Xilinx Vivado, Xilinx Vitis, FPGA, SVA, BookSim, Garnet
3w
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Senior SoC Subsystem and I/O Architect - LPU
California or Texas or Massachusetts
$184k-$357k/yr RemoteFull Time
8+ YOEBS, MS, or PhD in engineering or computer science and 8+ years of SoC, subsystem, I/O, interconnect, processor, accelerator, or high-performance systems architecture experience.
PCIe, CXL, NVLink, NVLink-C2C, UCIe, AXI, CHI, NoC, C++, SystemC, Python, MMUs/IOMMUs, RTL, DFT
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