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19 noc engineer jobs at 12 companies in Concord, CA

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SR ASIC Design Engineer - NoC & AXI Interconnect
Santa Clara, California, United States
$175k-$300k/yr OnsiteFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Experience in NoC design, AXI/ACE/APB interfaces, queuing, collaboration with architecture/IP/PD teams; Bachelors or Masters in computer or electrical engineering; Santa Clara, CA location; not eligible for visa sponsorship
SystemVerilog, Verilog, VCS, Perl, Python, Shell, NoC, AXI, ACE, APB, Queuing
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2w
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Principal NoC IP Micro-Architect
San Jose, California, United States
$210k-$299k/yr OnsiteFull Time
Altera
Altera: Manufacturer of field-programmable gate arrays and programmable logic devices.
15+ YOE15+ years in NoC IP and RTL design with SystemVerilog, strong RTL validation and SoC interconnect architecture experience; proficiency in C/C++/Perl/Python/TCL/Unix Shell; bachelor’s or master’s in EE/CE.
System Verilog, VCS, Synopsys, C, C++, Perl, Python, TCL, Unix Shell
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Senior RTL Designer - Interconnect/NoC Design
San Jose or United States
HybridFull Time
TylSemi
TylSemi: Building chiplet-native infrastructure for high-performance AI systems.
8+ YOEBS/MS in EE/CE with 8+ years digital IC design and 4+ years owning on-chip interconnect/NoC; deep SystemVerilog, AXI/CHI, CDC, NoC, top-level integration and register-map experience required.
AXI4, AXI4-Lite, AXI-Stream, CHI, AMBA CHI, ACE, SystemVerilog, SystemRDL, IP-XACT
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Senior RTL Engineer, Interconnect Design
San Francisco, California, United States
$225k-$445k/yr HybridFull Time
OpenAI
OpenAI: Develops artificial intelligence models and generative AI software services.
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, RDMA, RoCE, network-on-chip, NoC, FPGA, lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test
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Design Verification Engineer
San Jose, California, United States
$96k-$176k/yr OnsiteFull Time
Arrow Electronics
Arrow ElectronicsNYSE: ARW: Distributes electronic components and enterprise computing solutions globally.
5+ YOEExpertise in SV/UVM, AXI/NOC/Ethernet/PCIe/UCIe, ARM/RISC-V with C, regression and coverage closure; typically requires 5+ years' related experience and a 4-year degree (or equivalent).
SV, UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, NVMe, NAND, DDR
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Design Verification Engineer IV
San Jose, California, United States
$112k-$176k/yr OnsiteFull Time
Arrow Electronics
Arrow ElectronicsNYSE: ARW: Distributes electronic components and enterprise computing solutions globally.
6+ YOEExpertise in SystemVerilog/UVM, AXI/PCIe/Ethernet/NOC/UCIe protocols, CPU architectures (ARM, RISC-V) and C/C++; 6–8+ years verification experience; formal verification and scripting experience; ability to architect SoC verification environments.
SystemVerilog (SV), UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, C++
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Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
OnsiteFull Time
SiFive
SiFive: Designs and licenses high-performance RISC-V processor intellectual property.
Staff-level hardware engineer with experience designing interconnects, cache/coherency, RTL generators using Chisel/Scala; proficiency in Verilog/System Verilog/VHDL and hardware-software engineering practices; BS/MS in EE/CE/CS or equivalent.
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, TileLink, RISC-V, NoC, AXI, AHB, APB, CHI, Bluespec, Git, GitHub, Jira, Confluence
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Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
$179k-$219k/yr OnsiteFull Time
SiFive
SiFive: Designs and licenses high-performance RISC-V processor intellectual property.
Design and implement TileLink interconnect, cache controllers and RTL generators; knowledge of cache coherency, NoC/interconnects, bus protocols (AXI/AHB/APB/CHI), RTL (Verilog/SystemVerilog/VHDL), and strong software engineering skills (Scala/Chisel preferred).
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, TileLink, RISC-V, AXI, AHB, APB, CHI, Git, GitHub, Jira, Confluence
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Senior RTL Designer - Interconnect/NoC Design
San Jose or United States
HybridFull Time
TylSemi
TylSemi: Building chiplet-native infrastructure for high-performance AI systems.
8+ YOEBS/MS in EE/CE or equivalent,8+ years digital IC design with 4+ years owning on-chip interconnect/NoC; SystemVerilog skills; experience with AXI/CHI/ACE, CDC, top-level integration, and register-map flows.
SystemVerilog, SystemRDL, IP-XACT, AXI4, AXI4-Lite, AXI-Stream, CHI, ACE
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Custom SOC IP Verification Engineer
Santa Clara or Austin
$168k-$311k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
6+ YOE6+ years ASIC verification experience with fabric/interconnect/NoC, strong SystemVerilog and UVM skills, knowledge of interconnect protocols (AMBA AXI, CHI), scripting (Python, Perl, TCL), and degree in computer/electrical engineering or equivalent experience.
SystemVerilog, UVM, AMBA AXI, CHI, Python, Perl, TCL, Palladium, Veloce, SVA
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Principal Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
$231k-$283k/yr OnsiteFull Time
SiFive
SiFive: Designs and licenses high-performance RISC-V processor intellectual property.
Expertise in interconnects, cache/coherency, NoC and bus protocols (AXI, AHB, APB, CHI, CXL, UCIe); RTL design in Verilog/SystemVerilog/VHDL; experience with Chisel/FIRRTL/Scala preferred; BS/MS in EE/CE/CS or equivalent.
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, Git, GitHub, Jira, Confluence
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SoC Logic Design Engineer
Austin or Santa Clara or Hillsboro
$142k-$200k/yr HybridFull Time
Intel
IntelNasdaq: INTC: Designs and manufactures microprocessors and semiconductor components.
3+ YOEExperience in RTL/Verilog logic design, SoC integration, low-power and timing optimization, Clock Domain Crossing and NoC architectures, AMBA protocols; bachelor's or master's in EE/CE with relevant years of experience.
RTL, Verilog, AMBA, CHI, AXI, AHB, APB, Network-on-Chip (NoC), Clock Domain Crossing
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SoC Interconnect and Fabric RTL Designer
San Jose or Bangalore
HybridFull Time
TylSemi
TylSemi: Building chiplet-native infrastructure for high-performance AI systems.
8+ YOEBS/MS in Electrical/Computer Engineering; 8+ years digital IC design; 4+ years owning on-chip interconnect/NoC; expertise in AXI/CHI/ACE, SystemVerilog; NoC/IP integration; CDC; fabric RTL ownership.
SystemVerilog, AXI4, AXI4-Lite, AXI-Stream, CHI, ACE, NoC, AMBA, SystemRDL, IP-XACT, FIFOs, arbiters, address_decoders, arbiter, CDC
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Senior Network Operations Center (NOC) Engineer | Contact Center (Remote)
Dallas or Louisville or Irvine or Denver or Indianapolis or Grand Rapids or Lexington or Los Angeles or San Francisco
$81k-$100k/yr RemoteFull Time
Trace3
Trace3: Provides IT consulting and technology solutions for enterprise digital transformation.
Extensive hands-on experience with Cisco contact center and collaboration technologies, SIP/CUBE, VMware, scripting (PowerShell/Python/Bash), ServiceNow and LogicMonitor; Tier 3 incident ownership and on-call support in a 24x7 operations model.
ServiceNow, LogicMonitor, PowerShell, Python, Bash, VMware vSphere/ESXi, Cisco Unified Contact Center Enterprise (UCCE), ICM, Cisco Voice Portal (CVP/Call Studio), Finesse, CUIC, ECE, CUSP, Webex Contact Center, Webex Suite, Cisco Unified Communications Manager (CUCM), Cisco Unity Connection, Expressway, Cisco Voice Gateways, Cisco Unified Border Element (CUBE), SIP, IVR
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Manager of Field Applications Engineering, USA
Santa Clara or Austin
OnsiteFull Time
Baya Systems
Baya Systems: Designs semiconductor fabric IP and chiplet design software.
10+ YOE5+ MgmtBachelor's in EE/CE/STEM required; 10+ years in semiconductor/silicon IP/networking and 5+ years managing customer-facing engineering teams; deep NoC/AMBA/PCIe/CXL knowledge and EDA tool familiarity.
Synopsys, Cadence, Siemens
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AI/ML ASIC Architect
Milpitas, California, United States
$137k-$226k/yr HybridFull Time
Sandisk
SandiskNasdaq: SNDK: Designs and manufactures flash memory and data storage products.
7+ YOE7+ yrs experience in Computer/Electrical Engineering; 5+ yrs for Masters; 3+ yrs for PhD; architecture authoring experience; PCIe/UCIe/CXL, DMA subsystems know-how.
PCIe, UCIe, CXL, NoC, DMA, HBM, NVLink, CUDA
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Distinguished GPU Memory Simulation Architect
Santa Clara or United States
$320k-$489k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
18+ YOE18+ years experience, advanced degree or equivalent, deep GPU memory and NoC architecture knowledge, performance modeling and simulation expertise, strong programming in C/C++ and Python, and technical leadership experience.
C, C++, Python
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Lead SoC Architect - India
Sunnyvale or India
OnsiteFull Time
Bolt Graphics
Bolt Graphics: Designing high-efficiency graphics processors for professional rendering and simulation.
10+ YOERequires Bachelor's or Master's in EE/CE/CS, 10+ years SoC/ASIC experience, expertise in SoC subsystems (CPU/GPU/NPU, NoC, memory, PCIe), C/C++/SystemC modeling, RTL knowledge, and on-site presence in Sunnyvale.
C, C++, SystemC, Linux
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AI/ML ASIC Architect
Milpitas, California, United States
$194k-$322k/yr HybridFull Time
Sandisk
SandiskNasdaq: SNDK: Designs and manufactures flash memory and data storage products.
15+ YOE15+ years hands-on ASIC/SoC/IO architecture experience; strong PCIe/UCIe/CXL, DMA know-how; ML/LLM aware; memory hierarchy optimization; ARM/x86/RISC-V host interactions.
PCIe, UCIe, CXL, DMA, NoC, HBM, GPU, TPU, xPU, NVMe
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