5 noc engineer jobs at 5 companies in Fairfax, CA
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Senior RTL Engineer, Interconnect Design
San Francisco, California, United States
$225k-$445k/yr HybridFull Time
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, RDMA, RoCE, network-on-chip, NoC, FPGA, lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test
5d
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AV Engineer
San Francisco, California, United States
$100k-$120k/yr OnsiteFull Time
5+ YOERequires 5+ years of AV engineering or integration experience, Crestron programming, room automation, site build-outs, vendor management, networking fundamentals, and ability to pass a background check.
Crestron, Crestron NVX, Crestron DM, Extron, Q-SYS, Zoom Rooms, Microsoft Teams Rooms, Google Meet, QSC Q-SYS, Biamp, IP addressing, VLANs, QoS, multicast, NOC
5d
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Staff SoC RTL Engineer
Burlingame, California, United States
$175k-$230k/yr HybridFull Time
5+ YOERequires BS, MS, or Ph.D. in engineering, 5+ years of SoC/ASIC front-end design, SystemVerilog or Verilog, computer architecture, low-power design, subsystem integration, and VCS with Verilog/C co-simulation.
SystemVerilog, Verilog, VCS, Verilog/C Co-Simulation, FPGA, PCIe, UCIe, DDR, NoC
1mo
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Principal SoC Architect
Walnut Creek, California, United States
$168k-$300k/yr OnsiteFull Time
12+ YOEBachelor's degree in electrical or computer engineering; 12+ years in ARM-based SoC architecture and silicon development; experience with memory, IO virtualization, Ethernet, PCIe, memory subsystems, and NoC.
ARM, Ethernet, PCIe, NoC, RTL, Tcl, Perl, Python
15h
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Member of Technical Staff — On-Chip Interconnect & High-Speed Fabric Design
Palo Alto or Bangalore
OnsiteFull Time
5+ YOEBachelor's, master's, or PhD in electrical or computer engineering; 5+ years RTL design; advanced-node tapeout; AMBA, NoC, HSIO, SystemVerilog, Python, synthesis, timing, CDC, and PPA expertise.
AMBA, AXI4, AXI5, ACE, ACE-Lite, CHI, AHB, APB, AXI-Stream, PCIe, CXL.io, CXL.mem, CXL.cache, UCIe, SystemVerilog, Python, Xilinx, Xilinx Vivado, Xilinx Vitis, FPGA, SVA, BookSim, Garnet