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7 noc engineer jobs at 4 companies in Gustine, CA

4d
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Principal NoC IP Micro-Architect
San Jose, California, United States
$210k-$299k/yr OnsiteFull Time
Altera
Altera: Manufacturer of field-programmable gate arrays and programmable logic devices.
15+ YOE15+ years in NoC IP and RTL design with SystemVerilog, strong RTL validation and SoC interconnect architecture experience; proficiency in C/C++/Perl/Python/TCL/Unix Shell; bachelor’s or master’s in EE/CE.
System Verilog, VCS, Synopsys, C, C++, Perl, Python, TCL, Unix Shell
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3mo
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FPGA Silicon Design Engineer
San Jose, California, United States
$149k-$216k/yr OnsiteFull Time
Altera
Altera: Manufacturer of field-programmable gate arrays and programmable logic devices.
8+ YOEBachelor's degree in engineering/CS and 8+ years in RTL design with SystemVerilog/Verilog, Python, NoC, and cross-functional collaboration.
SystemVerilog, Verilog, Python, SpyGlass, Synthesis, STA, NoC, FPGA tools
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1mo
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Design Verification Engineer
San Jose, California, United States
$96k-$176k/yr OnsiteFull Time
Arrow Electronics
Arrow ElectronicsNYSE: ARW: Distributes electronic components and enterprise computing solutions globally.
5+ YOEExpertise in SV/UVM, AXI/NOC/Ethernet/PCIe/UCIe, ARM/RISC-V with C, regression and coverage closure; typically requires 5+ years' related experience and a 4-year degree (or equivalent).
SV, UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, NVMe, NAND, DDR
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2mo
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Lead RTL Design Engineer
Austin or Pittsburgh or San Jose
$160k-$250k/yr OnsiteFull Time
Efficient Computer
Efficient Computer: Developing ultra-low-power general-purpose processors for edge AI computing.
8+ YOE8+ years RTL design with tape-out ownership; SystemVerilog; on-chip networks, memory subsystems, NoC; low-power design; DV collaboration; silicon bring-up.
SystemVerilog, UPF, AXI, AHB, APB, TileLink, NoC, SDC, STA, ATPG, DFT, memory compiler
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1mo
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Design Verification Engineer IV
San Jose, California, United States
$112k-$176k/yr OnsiteFull Time
Arrow Electronics
Arrow ElectronicsNYSE: ARW: Distributes electronic components and enterprise computing solutions globally.
6+ YOEExpertise in SystemVerilog/UVM, AXI/PCIe/Ethernet/NOC/UCIe protocols, CPU architectures (ARM, RISC-V) and C/C++; 6–8+ years verification experience; formal verification and scripting experience; ability to architect SoC verification environments.
SystemVerilog (SV), UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, C++
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3d
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SoC Interconnect and Fabric RTL Designer
San Jose, California, United States
HybridFull Time
TylSemi
TylSemi: Building chiplet-native infrastructure for high-performance AI systems.
8+ YOEBS/MS in EE/Computer Engineering, 8+ years digital IC design with 4+ years owning on-chip interconnect/NoC or fabric architecture; strong SystemVerilog, AXI/CHI/NoC, CDC, integration, and register-map experience.
AXI4, AXI4-Lite, AXI-Stream, CHI, AMBA CHI, ACE, NoC, SystemVerilog, SystemRDL, IP-XACT
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1mo
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SoC Interconnect and Fabric RTL Designer
San Jose or Bangalore
HybridFull Time
TylSemi
TylSemi: Building chiplet-native infrastructure for high-performance AI systems.
8+ YOEBS/MS in Electrical/Computer Engineering; 8+ years digital IC design; 4+ years owning on-chip interconnect/NoC; expertise in AXI/CHI/ACE, SystemVerilog; NoC/IP integration; CDC; fabric RTL ownership.
SystemVerilog, AXI4, AXI4-Lite, AXI-Stream, CHI, ACE, NoC, AMBA, SystemRDL, IP-XACT, FIFOs, arbiters, address_decoders, arbiter, CDC
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