10 noc engineer jobs at 6 companies in Newman, CA
2w
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Senior RTL Designer - Interconnect/NoC Design
San Jose or United States
HybridFull Time
8+ YOEBS/MS in EE/CE with 8+ years digital IC design and 4+ years owning on-chip interconnect/NoC; deep SystemVerilog, AXI/CHI, CDC, NoC, top-level integration and register-map experience required.
AXI4, AXI4-Lite, AXI-Stream, CHI, AMBA CHI, ACE, SystemVerilog, SystemRDL, IP-XACT
3w
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Principal NoC IP Micro-Architect
San Jose, California, United States
$210k-$299k/yr OnsiteFull Time
15+ YOE15+ years in NoC IP and RTL design with SystemVerilog, strong RTL validation and SoC interconnect architecture experience; proficiency in C/C++/Perl/Python/TCL/Unix Shell; bachelor’s or master’s in EE/CE.
System Verilog, VCS, Synopsys, C, C++, Perl, Python, TCL, Unix Shell
1mo
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SoC Verification Engineer – NoC / UVM
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Expertise in SystemVerilog and UVM, ASIC/SoC verification, constraint-random and coverage-driven methodologies, formal verification (SVA); experience with Synopsys VCS and Cadence IES preferred; B.S. or M.S. in computer/electrical engineering.
SystemVerilog, UVM, OVM, VMM, Verilog, SystemVerilog Assertions (SVA), Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal, Magellan
2mo
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Design Verification Engineer
San Jose, California, United States
$96k-$176k/yr OnsiteFull Time
5+ YOEExpertise in SV/UVM, AXI/NOC/Ethernet/PCIe/UCIe, ARM/RISC-V with C, regression and coverage closure; typically requires 5+ years' related experience and a 4-year degree (or equivalent).
SV, UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, NVMe, NAND, DDR
1mo
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Design Verification Engineer IV
San Jose, California, United States
$112k-$176k/yr OnsiteFull Time
6+ YOEExpertise in SystemVerilog/UVM, AXI/PCIe/Ethernet/NOC/UCIe protocols, CPU architectures (ARM, RISC-V) and C/C++; 6–8+ years verification experience; formal verification and scripting experience; ability to architect SoC verification environments.
SystemVerilog (SV), UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, C++
2w
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Senior RTL Designer - Interconnect/NoC Design
San Jose or United States
HybridFull Time
8+ YOEBS/MS in EE/CE or equivalent,8+ years digital IC design with 4+ years owning on-chip interconnect/NoC; SystemVerilog skills; experience with AXI/CHI/ACE, CDC, top-level integration, and register-map flows.
SystemVerilog, SystemRDL, IP-XACT, AXI4, AXI4-Lite, AXI-Stream, CHI, ACE
2mo
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SoC Interconnect and Fabric RTL Designer
San Jose or Bangalore
HybridFull Time
8+ YOEBS/MS in Electrical/Computer Engineering; 8+ years digital IC design; 4+ years owning on-chip interconnect/NoC; expertise in AXI/CHI/ACE, SystemVerilog; NoC/IP integration; CDC; fabric RTL ownership.
SystemVerilog, AXI4, AXI4-Lite, AXI-Stream, CHI, ACE, NoC, AMBA, SystemRDL, IP-XACT, FIFOs, arbiters, address_decoders, arbiter, CDC
1d
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AI/ML ASIC Architect
Milpitas, California, United States
$194k-$322k/yr HybridFull Time
15+ YOEBachelors (or Masters/PhD) in Computer/Electrical Engineering with 15+ years architecture experience; deep expertise in PCIe/UCIe/CXL, DMA, SoC, HBM, ML/AI accelerator architecture; strong microarchitecture and system-level design skills.
UCIe, PCIe, CXL, DMA, NoC, FPGA, RTL, DV, Simulation, Emulation, Firmware, HBM, CUDA, NVLink, InfiniBand, RDMA, NVMe, NAND, AXI, MX format
2w
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SoC Interconnect Technology Team Lead
San Jose, California, United States
$398k-$538k/yr HybridFull Time
15+ YOE15+ years SoC architecture/design experience with interconnects, deep knowledge of coherent and non-coherent protocols, performance modeling, and proven leadership delivering complex SoCs to tape-out.
AMBA ACE, AMBA CHI, CCIX, CXL, AXI, NoC
1d
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AI/ML ASIC Architect
Milpitas, California, United States
$137k-$226k/yr HybridFull Time
3+ YOEBS+7/MS+5/PhD+3 experience in CE/EE with ASIC/SoC architecture experience; authoring architecture specs; PCIe/UCIe/CXL and DMA subsystems; ML/LLM and accelerator knowledge required.
UCIe, PCIe, CXL, DMA, HBM, NoC, FPGA, MX format, CUDA, NVLink, InfiniBand, RDMA, NVMe, NAND, AXI