21 noc engineer jobs at 13 companies in Oakley, CA
2mo
Save
Mark Applied
Hide
SR ASIC Design Engineer - NoC & AXI Interconnect
Santa Clara, California, United States
$175k-$300k/yr OnsiteFull Time
Experience in NoC design, AXI/ACE/APB interfaces, queuing, collaboration with architecture/IP/PD teams; Bachelors or Masters in computer or electrical engineering; Santa Clara, CA location; not eligible for visa sponsorship
SystemVerilog, Verilog, VCS, Perl, Python, Shell, NoC, AXI, ACE, APB, Queuing
2w
Save
Mark Applied
Hide
Senior RTL Designer - Interconnect/NoC Design
San Jose or United States
HybridFull Time
8+ YOEBS/MS in EE/CE with 8+ years digital IC design and 4+ years owning on-chip interconnect/NoC; deep SystemVerilog, AXI/CHI, CDC, NoC, top-level integration and register-map experience required.
AXI4, AXI4-Lite, AXI-Stream, CHI, AMBA CHI, ACE, SystemVerilog, SystemRDL, IP-XACT
3w
Save
Mark Applied
Hide
Principal NoC IP Micro-Architect
San Jose, California, United States
$210k-$299k/yr OnsiteFull Time
15+ YOE15+ years in NoC IP and RTL design with SystemVerilog, strong RTL validation and SoC interconnect architecture experience; proficiency in C/C++/Perl/Python/TCL/Unix Shell; bachelor’s or master’s in EE/CE.
System Verilog, VCS, Synopsys, C, C++, Perl, Python, TCL, Unix Shell
1mo
Save
Mark Applied
Hide
Senior RTL Engineer, Interconnect Design
San Francisco, California, United States
$225k-$445k/yr HybridFull Time
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, RDMA, RoCE, network-on-chip, NoC, FPGA, lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test
2mo
Save
Mark Applied
Hide
Design Verification Engineer
San Jose, California, United States
$96k-$176k/yr OnsiteFull Time
5+ YOEExpertise in SV/UVM, AXI/NOC/Ethernet/PCIe/UCIe, ARM/RISC-V with C, regression and coverage closure; typically requires 5+ years' related experience and a 4-year degree (or equivalent).
SV, UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, NVMe, NAND, DDR
1mo
Save
Mark Applied
Hide
Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
OnsiteFull Time
Staff-level hardware engineer with experience designing interconnects, cache/coherency, RTL generators using Chisel/Scala; proficiency in Verilog/System Verilog/VHDL and hardware-software engineering practices; BS/MS in EE/CE/CS or equivalent.
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, TileLink, RISC-V, NoC, AXI, AHB, APB, CHI, Bluespec, Git, GitHub, Jira, Confluence
3w
Save
Mark Applied
Hide
Custom SOC IP Verification Engineer
Santa Clara or Austin
$168k-$311k/yr OnsiteFull Time
6+ YOE6+ years ASIC verification experience with fabric/interconnect/NoC, strong SystemVerilog and UVM skills, knowledge of interconnect protocols (AMBA AXI, CHI), scripting (Python, Perl, TCL), and degree in computer/electrical engineering or equivalent experience.
SystemVerilog, UVM, AMBA AXI, CHI, Python, Perl, TCL, Palladium, Veloce, SVA
2w
Save
Mark Applied
Hide
SoC Logic Design Engineer
Austin or Santa Clara or Hillsboro
$142k-$200k/yr HybridFull Time
3+ YOEExperience in RTL/Verilog logic design, SoC integration, low-power and timing optimization, Clock Domain Crossing and NoC architectures, AMBA protocols; bachelor's or master's in EE/CE with relevant years of experience.
RTL, Verilog, AMBA, CHI, AXI, AHB, APB, Network-on-Chip (NoC), Clock Domain Crossing
1mo
Save
Mark Applied
Hide
Senior Network Operations Center (NOC) Engineer | Contact Center (Remote)
Dallas or Louisville or Irvine or Denver or Indianapolis or Grand Rapids or Lexington or Los Angeles or San Francisco
$81k-$100k/yr RemoteFull Time
Extensive hands-on experience with Cisco contact center and collaboration technologies, SIP/CUBE, VMware, scripting (PowerShell/Python/Bash), ServiceNow and LogicMonitor; Tier 3 incident ownership and on-call support in a 24x7 operations model.
ServiceNow, LogicMonitor, PowerShell, Python, Bash, VMware vSphere/ESXi, Cisco Unified Contact Center Enterprise (UCCE), ICM, Cisco Voice Portal (CVP/Call Studio), Finesse, CUIC, ECE, CUSP, Webex Contact Center, Webex Suite, Cisco Unified Communications Manager (CUCM), Cisco Unity Connection, Expressway, Cisco Voice Gateways, Cisco Unified Border Element (CUBE), SIP, IVR
4w
Save
Mark Applied
Hide
Manager of Field Applications Engineering, USA
Santa Clara or Austin
OnsiteFull Time
10+ YOE5+ MgmtBachelor's in EE/CE/STEM required; 10+ years in semiconductor/silicon IP/networking and 5+ years managing customer-facing engineering teams; deep NoC/AMBA/PCIe/CXL knowledge and EDA tool familiarity.
Synopsys, Cadence, Siemens
1d
Save
Mark Applied
Hide
AI/ML ASIC Architect
Milpitas, California, United States
$194k-$322k/yr HybridFull Time
15+ YOEBachelors (or Masters/PhD) in Computer/Electrical Engineering with 15+ years architecture experience; deep expertise in PCIe/UCIe/CXL, DMA, SoC, HBM, ML/AI accelerator architecture; strong microarchitecture and system-level design skills.
UCIe, PCIe, CXL, DMA, NoC, FPGA, RTL, DV, Simulation, Emulation, Firmware, HBM, CUDA, NVLink, InfiniBand, RDMA, NVMe, NAND, AXI, MX format
3mo
Save
Mark Applied
Hide
Senior Performance Modeling Architect, CPU Fabric and LLC
Santa Clara, California, United States
$152k-$288k/yr OnsiteFull Time
5+ YOEMaster's or PhD in CE/EE/CS (or equivalent) with 5+ years experience; deep knowledge of CPU microarchitecture, cache coherency, NoC topologies; experience with C++/SystemC and Python; benchmarking and performance analysis experience.
C++, SystemC, Python, SPEC, MLPerf
1mo
Save
Mark Applied
Hide
Lead SoC Architect - India
Sunnyvale or India
OnsiteFull Time
10+ YOERequires Bachelor's or Master's in EE/CE/CS, 10+ years SoC/ASIC experience, expertise in SoC subsystems (CPU/GPU/NPU, NoC, memory, PCIe), C/C++/SystemC modeling, RTL knowledge, and on-site presence in Sunnyvale.
C, C++, SystemC, Linux
2w
Save
Mark Applied
Hide
SoC Interconnect Technology Team Lead
San Jose, California, United States
$398k-$538k/yr HybridFull Time
15+ YOE15+ years SoC architecture/design experience with interconnects, deep knowledge of coherent and non-coherent protocols, performance modeling, and proven leadership delivering complex SoCs to tape-out.
AMBA ACE, AMBA CHI, CCIX, CXL, AXI, NoC
Explore Jobs