2mo
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SR ASIC Design Engineer - NoC & AXI Interconnect
Santa Clara, California, United States
$175k-$300k/yr OnsiteFull Time
Experience in NoC design, AXI/ACE/APB interfaces, queuing, collaboration with architecture/IP/PD teams; Bachelors or Masters in computer or electrical engineering; Santa Clara, CA location; not eligible for visa sponsorship
SystemVerilog, Verilog, VCS, Perl, Python, Shell, NoC, AXI, ACE, APB, Queuing
6d
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Principal NoC IP Micro-Architect
San Jose, California, United States
$210k-$299k/yr OnsiteFull Time
15+ YOE15+ years in NoC IP and RTL design with SystemVerilog, strong RTL validation and SoC interconnect architecture experience; proficiency in C/C++/Perl/Python/TCL/Unix Shell; bachelor’s or master’s in EE/CE.
System Verilog, VCS, Synopsys, C, C++, Perl, Python, TCL, Unix Shell
1mo
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SoC Verification Engineer – NoC / UVM
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Expertise in SystemVerilog and UVM, ASIC/SoC verification, constraint-random and coverage-driven methodologies, formal verification (SVA); experience with Synopsys VCS and Cadence IES preferred; B.S. or M.S. in computer/electrical engineering.
SystemVerilog, UVM, OVM, VMM, Verilog, SystemVerilog Assertions (SVA), Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal, Magellan
3mo
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FPGA Silicon Design Engineer
San Jose, California, United States
$149k-$216k/yr OnsiteFull Time
8+ YOEBachelor's degree in engineering/CS and 8+ years in RTL design with SystemVerilog/Verilog, Python, NoC, and cross-functional collaboration.
SystemVerilog, Verilog, Python, SpyGlass, Synthesis, STA, NoC, FPGA tools
1mo
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Design Verification Engineer
San Jose, California, United States
$96k-$176k/yr OnsiteFull Time
5+ YOEExpertise in SV/UVM, AXI/NOC/Ethernet/PCIe/UCIe, ARM/RISC-V with C, regression and coverage closure; typically requires 5+ years' related experience and a 4-year degree (or equivalent).
SV, UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, NVMe, NAND, DDR
2mo
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Lead RTL Design Engineer
Austin or Pittsburgh or San Jose
$160k-$250k/yr OnsiteFull Time
8+ YOE8+ years RTL design with tape-out ownership; SystemVerilog; on-chip networks, memory subsystems, NoC; low-power design; DV collaboration; silicon bring-up.
SystemVerilog, UPF, AXI, AHB, APB, TileLink, NoC, SDC, STA, ATPG, DFT, memory compiler
1mo
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Design Verification Engineer IV
San Jose, California, United States
$112k-$176k/yr OnsiteFull Time
6+ YOEExpertise in SystemVerilog/UVM, AXI/PCIe/Ethernet/NOC/UCIe protocols, CPU architectures (ARM, RISC-V) and C/C++; 6–8+ years verification experience; formal verification and scripting experience; ability to architect SoC verification environments.
SystemVerilog (SV), UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, C++
3w
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Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
OnsiteFull Time
Staff-level hardware engineer with experience designing interconnects, cache/coherency, RTL generators using Chisel/Scala; proficiency in Verilog/System Verilog/VHDL and hardware-software engineering practices; BS/MS in EE/CE/CS or equivalent.
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, TileLink, RISC-V, NoC, AXI, AHB, APB, CHI, Bluespec, Git, GitHub, Jira, Confluence
2w
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Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
$179k-$219k/yr OnsiteFull Time
Design and implement TileLink interconnect, cache controllers and RTL generators; knowledge of cache coherency, NoC/interconnects, bus protocols (AXI/AHB/APB/CHI), RTL (Verilog/SystemVerilog/VHDL), and strong software engineering skills (Scala/Chisel preferred).
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, TileLink, RISC-V, AXI, AHB, APB, CHI, Git, GitHub, Jira, Confluence
1mo
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Sr Memory Subsystem Verification Engineer
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Expert in pre-silicon verification for NoC and DRAM memory controller IPs, strong SystemVerilog/UVM skills, simulation and formal tool experience, verification lifecycle ownership, mentoring ability, and relevant engineering degree.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, VC Formal, JasperGold, Questa Formal
1w
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Custom SOC IP Verification Engineer
Santa Clara or Austin
$168k-$311k/yr OnsiteFull Time
6+ YOE6+ years ASIC verification experience with fabric/interconnect/NoC, strong SystemVerilog and UVM skills, knowledge of interconnect protocols (AMBA AXI, CHI), scripting (Python, Perl, TCL), and degree in computer/electrical engineering or equivalent experience.
SystemVerilog, UVM, AMBA AXI, CHI, Python, Perl, TCL, Palladium, Veloce, SVA
2w
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Principal Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
$231k-$283k/yr OnsiteFull Time
Expertise in interconnects, cache/coherency, NoC and bus protocols (AXI, AHB, APB, CHI, CXL, UCIe); RTL design in Verilog/SystemVerilog/VHDL; experience with Chisel/FIRRTL/Scala preferred; BS/MS in EE/CE/CS or equivalent.
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, Git, GitHub, Jira, Confluence
5d
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SoC Interconnect and Fabric RTL Designer
San Jose, California, United States
HybridFull Time
8+ YOEBS/MS in EE/Computer Engineering, 8+ years digital IC design with 4+ years owning on-chip interconnect/NoC or fabric architecture; strong SystemVerilog, AXI/CHI/NoC, CDC, integration, and register-map experience.
AXI4, AXI4-Lite, AXI-Stream, CHI, AMBA CHI, ACE, NoC, SystemVerilog, SystemRDL, IP-XACT
1mo
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SoC Interconnect and Fabric RTL Designer
San Jose or Bangalore
HybridFull Time
8+ YOEBS/MS in Electrical/Computer Engineering; 8+ years digital IC design; 4+ years owning on-chip interconnect/NoC; expertise in AXI/CHI/ACE, SystemVerilog; NoC/IP integration; CDC; fabric RTL ownership.
SystemVerilog, AXI4, AXI4-Lite, AXI-Stream, CHI, ACE, NoC, AMBA, SystemRDL, IP-XACT, FIFOs, arbiters, address_decoders, arbiter, CDC
3mo
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Technical Lead, Design Verification
Santa Clara, California, United States
$159k-$238k/yr OnsiteFull Time
Lead verification for SoCs, develop UVM environments, mentor engineers, strong SystemVerilog, Python, ARM/NoC expertise.
SystemVerilog, UVM, Python, Xcelium, Questa, VCS
2w
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Manager of Field Applications Engineering, USA
Santa Clara or Austin
OnsiteFull Time
10+ YOE5+ MgmtBachelor's in EE/CE/STEM required; 10+ years in semiconductor/silicon IP/networking and 5+ years managing customer-facing engineering teams; deep NoC/AMBA/PCIe/CXL knowledge and EDA tool familiarity.
Synopsys, Cadence, Siemens
2mo
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AI/ML ASIC Architect
Milpitas, California, United States
$137k-$226k/yr HybridFull Time
7+ YOE7+ yrs experience in Computer/Electrical Engineering; 5+ yrs for Masters; 3+ yrs for PhD; architecture authoring experience; PCIe/UCIe/CXL, DMA subsystems know-how.
PCIe, UCIe, CXL, NoC, DMA, HBM, NVLink, CUDA
2mo
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Senior Performance Modeling Architect, CPU Fabric and LLC
Santa Clara, California, United States
$152k-$288k/yr OnsiteFull Time
5+ YOEMaster's or PhD in CE/EE/CS (or equivalent) with 5+ years experience; deep knowledge of CPU microarchitecture, cache coherency, NoC topologies; experience with C++/SystemC and Python; benchmarking and performance analysis experience.
C++, SystemC, Python, SPEC, MLPerf
2mo
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AI/ML ASIC Architect
Milpitas, California, United States
$194k-$322k/yr HybridFull Time
15+ YOE15+ years hands-on ASIC/SoC/IO architecture experience; strong PCIe/UCIe/CXL, DMA know-how; ML/LLM aware; memory hierarchy optimization; ARM/x86/RISC-V host interactions.
PCIe, UCIe, CXL, DMA, NoC, HBM, GPU, TPU, xPU, NVMe
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