4w
Save
Mark Applied
Hide
NoC Interconnect Design Engineer and Architect
San Diego, California, United States
$164k-$246k/yr OnsiteFull Time
6+ YOEBachelor's +6 / Master's +5 / PhD +4 years ASIC design experience; knowledge of AHB/AXI/CHI and NoC, ASIC flow (synthesis, STA, Lint), RTL/FPGA and post-silicon debug; strong architecture, performance/power analysis and communication skills.
AHB, AXI, CHI, RTL, FPGA, synthesis tools, STA, Lint, power tools
1w
Save
Mark Applied
Hide
Lead AI NOC Engineer
Somerville or Fort Mill or Austin or Boston or New York or Tempe or San Diego
$94k-$171k/yr HybridFull Time
8+ YOE5+ Mgmt8+ years in IT operations/SRE, 5+ years leading incident management; bachelor\u0002s or equivalent; hands-on Dynatrace and ServiceNow experience; cloud (AWS/Azure/GCP) expertise; ITIL/SRE/AIOps experience.
Dynatrace, ServiceNow, AWS, Azure, GCP
1mo
Save
Mark Applied
Hide
NoC Interconnect Design Engineer and Architect
San Diego, California, United States
$116k-$173k/yr OnsiteFull Time
2+ YOEBachelor's degree +2 yrs (or Master's +1 yr or PhD) in Science/Engineering; experience with bus protocols (AHB, AXI, CHI), ASIC flow (synthesis, STA, Lint), RTL/FPGA and performance/power/area analysis.
AHB, AXI, CHI, NoC, RTL, FPGA, STA, Lint
1mo
Save
Mark Applied
Hide
Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer
San Diego, California, United States
$140k-$210k/yr OnsiteFull Time
4+ YOEBachelor's degree in engineering (or higher) plus multi-year ASIC/RTL design experience (4+ years with Bachelor's; 3+ with Master's; 2+ with PhD). Experience with high-speed memory subsystems (LPDDR, HBM), NoC, cache/SRAM controllers, and hardware architecture.
RTL, Synthesis, Timing Closure, Gate Level Simulations, Power Analysis
1w
Save
Mark Applied
Hide
Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer
San Diego, California, United States
$140k-$210k/yr OnsiteFull Time
5+ YOEBachelor’s in EE/CE required (Master's preferred); 5+ years ASIC/RTL design experience; hardware architecture experience; experience with high-speed memory subsystems (HBM/LPDDR/DDR) and cache/NoC controllers.
1mo
Save
Mark Applied
Hide
Infra Systems Physical Architect
San Diego, California, United States
$140k-$210k/yr OnsiteFull Time
6+ YOEBachelor's +6 years (or Master's +5 or PhD +4) in Science/Engineering, 5+ years ASIC/NoC/physical architecture experience, expertise in physical design, timing, power, floorplanning, clocking, and scripting (Python, PERL, TCL).
NoC, System on Chip (SoC), DDR, AMBA Protocol, Design Compiler, Fusion Compiler, Genus, Primetime, Prime power, Innovus, TCL, Python, PERL, Linux/Unix shell, C