52 packaging design engineer jobs at 20 companies in Bastrop, TX
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Entry Level Packaging Systems Design Engineer I (Start Summer 2027)
Austin, Texas, United States
$78k-$82k/yr FieldFull Time
0+ YOEBachelor’s degree in mechanical, packaging, industrial, or manufacturing engineering; 0–3 years of relevant experience or schooling; MS Office, MS Project, and AutoCAD familiarity; strong communication and problem-solving skills.
Microsoft Office, Microsoft Project, AutoCAD
1mo
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Advanced Packaging Engineer
North America or California or Austin or Boston
$250k-$400k/yr HybridFull Time
Experience designing or developing processes for complex packages; first-principles problem solving. Preferred: heterogeneous materials, high-TDP packages, compound semiconductors, optics, interposers, flip-chip integration, or large substrates.
2w
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Package Layout Design Engineer , Annapurna Labs - AI Silicon Packaging
Tempe or Austin or Cupertino
$136k-$213k/yr OnsiteFull Time
5+ YOEBachelor's degree in electrical engineering or related field and 5+ years of IC package layout and physical design experience. Requires package layout tools, advanced packaging, DFM, and physical verification expertise.
Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, Python, Perl, ARM, TCL, Skill, Ravel, DRC
3w
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Materials Engineer, Packaging Product Design
Austin, Texas, United States
OnsiteFull Time
Collaborates on structural packaging design and execution, balancing customer experience, product protection, sustainability, and cross-functional design requirements.
1mo
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AI Automation Design Packaging Lead
Austin, Texas, United States
$163k-$244k/yr HybridFull Time
Technical leader to develop and deploy AI-driven packaging design automation. Requires bachelor's or master's in EE/CE/CS, experience with EDA tools, scripting (Python/Tcl/SKILL/C++), AI/ML frameworks, and cross-functional leadership.
Cadence APD/SIP, Siemens Xpedition, Synopsys 3DIC/Compiler, Python, Tcl, SKILL, C++, PyTorch, TensorFlow
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Package Design Methodology Engineer
Santa Clara or Austin or California
$136k-$265k/yr HybridFull Time
5+ YOEBS or equivalent and 5+ years developing package design flows; strong Python/C++ skills; experience applying AI/ML and LLMs in engineering workflows; solid VLSI package design fundamentals.
Python, C++, LLMs, EDA, AI/ML
4w
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Package Design Engineer
San Jose or Austin or Fort Collins
$122k-$195k/yr OnsiteFull Time
6+ YOEBSEE with 8+ years or MSEE with 6+ years in flip-chip BGA package design; knowledge of package signal and power integrity; Cadence APD and Cadence SKILL experience preferred; project management and collaboration skills.
Cadence APD, Cadence SKILL
1mo
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Package Design Methodology Engineer
Santa Clara or Austin or California
$136k-$265k/yr HybridFull Time
5+ YOEBS in computer science, electrical engineering, or related field; 5+ years developing scalable package design flows and methodologies; Python or C++; AI/ML engineering experience; VLSI package electrical fundamentals.
Python, C++, VLSI, EDA, LLMs
2mo
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Staff Package Design Engineer
Austin or Tempe
HybridFull Time
4+ YOE4+ years package CAD/layout or substrate design experience (6+ preferred); strong background in FCBGA, SiP, WLCSP, power modules; proficiency with Cadence Allegro Package Designer or Siemens Xpedition; BS/MS in EE, microelectronics, materials, or related field.
Cadence Allegro Package Designer, Siemens Xpedition Substrate Integrator
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Package Design Methodology Engineer
Santa Clara or Austin or United States
$136k-$265k/yr HybridFull Time
5+ YOEBS in CS/EE or equivalent,5+ years developing package design flows/methodologies,proficiency in Python and/or C++,knowledge of VLSI package electrical fundamentals,experience applying AI/ML or LLMs in engineering workflows.
Python, C++, LLMs, EDA
2mo
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Sr. Engineer, Package Design
Santa Clara or Austin or Toronto or New Taipei City
$100k-$500k/yr HybridFull Time
3+ YOE3+ years experience with Cadence Allegro PCB Designer, PCB routing and BGA design, signal and power integrity knowledge, strong communication and cross-discipline collaboration skills.
Cadence Allegro PCB Designer
3mo
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Sr. IC Package Design Engineer (Silicon Engineering)
Austin or Irvine
OnsiteFull Time
5+ YOEBachelor's degree in electrical/computer engineering or physics; 5+ years IC package design experience; strong SI/PI, RF, and CAD tool proficiency.
Cadence APD+/SIP, SIWave, HFSS, ADS, Package design tools
4w
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Senior IC Package Design Engineer - TeraWave
San Diego or Austin or California
$230k-$323k/yr OnsiteFull Time
7+ YOEBachelor's in EE or related,7+ years industry experience delivering IC packaging,expertise with HFSS/EMX/Momentum,Cadence Allegro experience preferred,RF/mmWave and power/signal integrity expertise,U.S. work authorization required.
HFSS, EMX, Momentum, Cadence Allegro
3mo
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Design & Verification Engineer, Analog Power Management (7682) (Austin, TX, US)
Austin, Texas, United States
$120k-$170k/yr OnsiteFull Time
7+ YOEMSEE with 7+ years in hands-on power management design/verification; SIMPLIS knowledge; PCB design/layout in PM; IC design/packaging familiarity; strong teamwork; power delivery modeling
SIMPLIS, PCB Design, Power Delivery Modeling
3w
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Principal EDA R&D Engineer, Advanced Packaging
Austin, Texas, United States
$166k-$249k/yr OnsiteFull Time
10+ YOEBachelor's or master's degree or equivalent experience; 10+ years in EDA software development; expertise in package substrate design, automation, computational geometry, and programming with Python or TCL.
C++, Python, TCL, ODB++
3w
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Physical Design - SOC Top Lead
San Jose or Pittsburgh or Austin
$200k-$250k/yr OnsiteFull Time
8+ YOEEnd-to-end SOC top ownership including full-chip integration, timing closure, power/PDN analysis, physical verification, SI, clock/reset, DFT, package co-design, and tapeout readiness; advanced degree in EE and extensive PD experience.
Innovus, ICC2, Tempus, PrimeTime, RedHawk, Calibre, Voltus, TCL, shell, python
2w
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PCB Design Engineering Section Lead
Hudson or Fort Wayne or Austin
$133k-$226k/yr OnsiteFull Time
Bachelor's degree in engineering, broad military electronics packaging design experience, organizational leadership, strong PCB design background, communication skills, and ability to obtain Secret clearance.
Cadence Allegro, IPC
6d
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Director of Package Design
Mountain View or Redmond or Hillsboro or Austin or Raleigh
$143k-$275k/yr HybridFull Time
3+ YOERequired: doctorate plus 3+ years, master's plus 6+ years, bachelor's plus 8+ years, or equivalent. Preferred: 15+ years semiconductor package experience and advanced packaging, CAD, simulation, supplier, and manufacturing expertise.
Cadence Allegro, EDA, BGA
2mo
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Mechanical Engineer, Staff to Principal level
Austin, Texas, United States
$110k-$183k/yr OnsiteFull Time
8+ YOEExperienced mechanical design engineer for high-power electrical equipment; strong busbar, wire-harness, board-packaging, insulation coordination, manufacturability, FEA/CFD, and SolidWorks skills; mentoring experience.
SolidWorks, FEA, CFD, CNC
3w
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3D-IC Application Engineer
Austin or Boulder or Fremont or San Diego or Santa Clara or Wilsonville
$125k-$251k/yr HybridFull Time
4+ YOEMSEE/BSEE and 4+ years of design experience with advanced IC package or interposer layout. Requires package design tools, scripting, Windows/Linux, and strong presentation and customer skills.
Innovator 3D IC Layout, Innovator3D IC Integrator, Xpedition, Calibre, HyperLynx, Cadence APD/SiP, Siemens XSI/i3DI, Cadence OrbitIO/ISP, Synopsys 3DIC Compiler, Microsoft Excel, TSMC InFO, CoWoS, Intel EMIB, Foveros, ASE FoCUS, Amkor SWIFT, Samsung I/H/X-Cube, Verilog, LEF/DEF, GDS, OASIS, Sigrity, SIWave, ADS, Microsoft Word, Microsoft PowerPoint, VBS, Python, Tcl, Perl, Windows, Linux